Datasheet

Section 5 Interrupt Controller

Rev. 6.00 Mar. 18, 2010 Page 136 of 982

REJ09B0054-0600

IRQn

input pin

IRQnF

Note: n = 7 to 0

Figure 5.3 Set Timing for IRQnF

The detection of IRQn interrupts does not depend on whether the relevant pin has been set for

input or output. However, when a pin is used as an external interrupt input pin, do not clear the

corresponding DDR to 0; and use the pin as an I/O pin for another function. IRQnF interrupt

request flag is set to 1 when the setting condition is satisfied, regardless of IER settings.

Accordingly, refer to only necessary flags.

5.4.2 Internal Interrupts

Internal interrupts that are requested from the on-chip peripheral modules have the following

features.

• For each on-chip peripheral module, there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts, and they are masked

independently. If the enable bit is set to 1 for a particular interrupt source, an interrupt request

is issued to the interrupt controller.

• The interrupt priority level can be set with IPR.

• TPU and SCI interrupt requests can activate the DMAC* or DTC. When the DMAC* or DTC

is activated by the interrupt request, the interrupt control mode and CPU interrupt mask bits are

disregarded.

Note: * Supported only by the H8S/2239 Group.

5.4.3 Interrupt Exception Handling Vector Table

Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.

For default priorities, the lower the vector number, the higher the priority.

Priorities among modules can be set by means of the IPR. Modules set at the same priority will

conform to their default priorities. Priorities within a module are fixed.