Datasheet

Section 5 Interrupt Controller
Rev. 6.00 Mar. 18, 2010 Page 131 of 982
REJ09B0054-0600
5.3.2 IRQ Enable Register (IER)
IER controls the enabling and disabling of interrupt requests IRQn (n = 7 to 0).
Bit Bit Name
Initial
Value R/W Description
7 IRQ7E 0 R/W IRQ7 Enable
The IRQ7 interrupt request is enabled when this bit is 1.
6 IRQ6E 0 R/W IRQ6 Enable
The IRQ6 interrupt request is enabled when this bit is 1.
5 IRQ5E 0 R/W IRQ5 Enable
The IRQ5 interrupt request is enabled when this bit is 1.
4 IRQ4E 0 R/W IRQ4 Enable
The IRQ4 interrupt request is enabled when this bit is 1.
3 IRQ3E 0 R/W IRQ3 Enable
The IRQ3 interrupt request is enabled when this bit is 1.
2 IRQ2E 0 R/W IRQ2 Enable
The IRQ2 interrupt request is enabled when this bit is 1.
1 IRQ1E 0 R/W IRQ1 Enable
The IRQ1 interrupt request is enabled when this bit is 1.
0 IRQ0E 0 R/W IRQ0 Enable
The IRQ0 interrupt request is enabled when this bit is 1.
5.3.3 IRQ Sense Control Registers H and L (ISCRH and ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQn (n = 7 to 0).
Specifiable sources are the falling edge, rising edge, or both edge detection, and level sensing.