Datasheet

Section 5 Interrupt Controller
Rev. 6.00 Mar. 18, 2010 Page 128 of 982
REJ09B0054-0600
A block diagram of the interrupt controller is shown in figure 5.1.
SYSCR
NMI input
IRQ input
Internal interrupt
request
SWDTEND to TEI3
NMIEG
INTM1, INTM0
NMI input unit
IRQ input unit
ISR
ISCR IER
IPR
Interrupt controller
Priority
determination
Interrupt
request
Vector number
I
I2 to I0
CCR
EXR
CPU
ISCR:
IER:
ISR:
IPR:
SYSCR:
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register
System control register
Legend:
Figure 5.1 Block Diagram of Interrupt Controller