Datasheet

Section 4 Exception Handling
Rev. 6.00 Mar. 18, 2010 Page 121 of 982
REJ09B0054-0600
4.3 Reset
A reset has the highest exception priority.
When the RES or MRES pin goes low, all processing halts and this LSI enters the reset. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules. The
interrupt control mode is 0 immediately after reset.
When the RES or MRES pin goes high from the low state, this LSI starts reset exception handling.
The chip can also be reset by overflow of the watchdog timer. For details see section 13,
Watchdog Timer (WDT).
4.3.1 Reset Types
The power-on reset and the manual reset are available as the reset.
Table 4.3 lists the reset types. When the power is supplied, select the power-on reset.
Both the power-on reset and the manual reset initialize the internal state of the CPU. The power-
on reset initializes all registers in on-chip peripheral modules. The manual reset initializes the
registers in on-chip peripheral modules except the bus controller and the I/O ports. The state of the
bus controller and the I/O ports are maintained.
At the manual reset, the on-chip peripheral modules are initialized. Thus, the ports that are used as
I/O pins for the on-chip peripheral modules are changed to the ports controlled by the DDR and
the DR.
Table 4.3 Reset Types
Condition
to Enter Reset
Internal State
Reset MRES RES CPU Internal Peripheral Modules
Power-on reset × Low Initialized Initialized
Manual reset Low High Initialized Initialized except the bus controller and the
I/O ports
Legend: ×:Don’t care
The power-on reset and the manual reset are also available for the reset by the watchdog timer.
To enable the MRES pin, set the MRESE bit in SYSCR to 1.