Datasheet

Rev. 6.00 Mar. 18, 2010 Page xvi of lx
REJ09B0054-0600
Item Page Revision (See Manual for Details)
16.6 Usage Notes
Figure 16.22 Flowchart and
Timing of Start Condition
Instruction Issuance for
Retransmission
681 Figure amended
SDA
IRIC
SCL
ACK
Bit 7
Data output
[3] (Restart) Start condition instruction issuance
[4] IRIC determination
[5] ICDR write (next transmit data)
[2] Detemination of SCL = Low
[1] IRIC determination
Start condition
(retransmission)
9
Figure 16.23 Timing of Stop
Condition Issuance
682 Figure amended
Stop condition
SCL
IRIC
[1] Determination of SCL = low
9th clock
VIH
High period secured
[2] Stop condition instruction issuance
SDA
As waveform rise is late,
SCL is detected as low
Figure 16.25 ICDR Read
and ICCR Access Timing in
Slave Transmit Mode
683 Figure amended
SDA
R/W
Waveforms if
problem occurs
Bit 7
ICDR write
Data transmission
Period when ICDR reads and ICCR
reads and writes are prohibited
(6 system clock cycles)
Detection of 9th clock
cycle rising edge
A
8 9
SCL
TRS bit
Address received
17.2 Input/Output Pins
Table 17.1 Pin Configuration
691 Table amended
Pin Name Symbol I/O Function
Analog power supply pin AV
CC
Input Analog block power supply and reference
voltage
Analog ground pin AV
SS
Input Analog block ground and reference voltage
Reference voltage pin Vref Input Reference voltage for A/D conversion
Analog input pin 0
AN0
*
Input
Analog input pin 1 AN1
*
Input
Group 0 analog input pins
Note added
Note: * In the case of the H8S/2239 Group, H8S/2227
Group, H8S/2238R, and H8S/2236R, AN0 and
AN1 may be used only when Vcc = AVcc.