Datasheet

Section 3 MCU Operating Modes
Rev. 6.00 Mar. 18, 2010 Page 109 of 982
REJ09B0054-0600
3.4 Memory Map in Each Operating Mode
Figures 3.1 to 3.9 show the memory map in each operating mode.
Modes 4 and 5
(advanced extended modes
with on-chip ROM disabled)
Mode 6
(advanced extended mode
with on-chip ROM enabled)
Mode 7
(advanced single-chip mode)
External address
space
Note: * Extermal addresses can be accessed by clearing the RAME bit in SYSCR to 0.
External address
space
Internal I/O registers
On-chip RAM*
External address
space
External address
space
External address
space
On-chip RAM*On-chip RAM*
On-chip ROM
On-chip ROM
Internal I/O registersInternal I/O registers
Internal I/O registers
On-chip RAM*
External address
space
On-chip RAM
Internal I/O registers
Internal I/O registers
On-chip RAM
H'000000
H'FFB000
H'FFEFC0
H'040000
H'000000
H'03FFFF
H'000000
H'FFB000
H'FFEFBF
H'FFFF40
H'FFFF60
H'FFFFC0
H'FFFFFF
H'FFF800
H'FFB000
H'FFEFC0
H'FFFF40
H'FFFF60 H'FFFF60
H'FFFFC0
H'FFFFFF
H'FFF800
H'FFFF3F
H'FFFFFF
H'FFF800
H'FFFFC0
Figure 3.1 H8S/2258 Memory Map in Each Operating Mode