Datasheet

Rev. 6.00 Mar. 18, 2010 Page xiv of lx
REJ09B0054-0600
Item Page Revision (See Manual for Details)
11.3.1 Timer Control
Register (TCR)
367 Table amended
Bit Bit Name Initial Value R/W Description
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g.
φ
/4 both edges =
φ
/2 rising
edge). If phase counting mode is used on channels 1,
2, 4
*
, and 5
*
, this setting is ignored and the phase
counting mode setting has priority. Internal clock edge
selection is valid when the input clock is /4 or slower.
When the input clock is
φ
/1 or when
overflow/underflow of another channel is selected,
this setting is ignored and the input clock is counted at
the falling edge of
φ
.
00: Count at rising edge
01: Count at falling edge
1 : Count at both edges
Legend:
×
: Don’t care
13.3.1 Timer Counter
(TCNT)
468 Description added
TCNT is an 8-bit readable/writable up-counter. TCNT is
initialized to H'00 when the TME bit in TCSR is cleared to 0.
To initialize TCNT to H'00 while the timer is operating, write
H'00 to TCNT directly. See 13.6.7, Notes on Initializing
TCNT by Using the TME Bit.
13.6.3 Changing Value of
PSS or CKS2 to CKS0
479 Description amended
If the PSS or CKS0 to CKS2 bits in TCSR are written to
while the WDT is operating, errors could occur in the
incrementation. Software must be used to stop the watchdog
timer (by clearing the TME bit to 0) before changing the
value of the PSS or CKS0 to CKS2 bits.
13.6.7 Notes on Initializing
TCNT by Using the TME Bit
479 13.6.7 added
15.3.8 Smart Card Mode
Register (SCMR)
570 Table amended
Bit Bit Name
Initial
Value R/W Description
7 to 4 — All 1 — Reserved
These bits are always read as 1, and cannot be
modified.
3 SDIR 0 R/W Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer data
format is 8 bits. Except in the case of 7-bit data in
asynchronous mode, either LSB-first or MSB-first
may be selected regardless of the serial
communication mode. For 7-bit data, set this bit to
0 to select LSB-first in transfer.