Datasheet

Section 2 CPU
Rev. 6.00 Mar. 18, 2010 Page 67 of 982
REJ09B0054-0600
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
Exception vector 1
Exception vector 2
Exception
vector table
Figure 2.1 Exception Vector Table (Normal Mode)
PC
(16 bits)
PC
(16 bits)
SP
SP EXR
*
1
Reserved
*
1
*
3
CCR
CCR
*
3
(SP
*
2
)
1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Notes:
(b) Exception Handling(a) Subroutine Branch
Figure 2.2 Stack Structure in Normal Mode
2.2.2 Advanced Mode
• Address Space
Linear access is provided to a maximum 16-Mbyte address space.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.