Datasheet

Section 1 Overview
Rev. 6.00 Mar. 18, 2010 Page 58 of 982
REJ09B0054-0600
Pin No.
Type Symbol
TFP-100B
TFP-100BV
TFP-100G
TFP-100GV
FP-100B
*
1
FP-100BV
*
1
FP-100A
*
2
FP-100AV
*
2
I/O Function
System
control
BREQ 75 78 Input Used by an external bus master to request the
bus mastership to this LSI.
BACK 74 77 Output Indicates that the bus mastership has been
granted to an external bus master.
FEW 66 69 Input Enables/disables programming the flash
memory.
Interrupts NMI
*
3
60 63 Input Nonmaskable interrupt pin. If this pin is not used,
it should be fixed-high.
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
92
91
81
78
72
75
40
38
95
94
84
81
75
78
43
41
Input These pins request a maskable interrupt.
Address bus A23 to A0 37 to 15,
13
40 to 18, 16 Output Outputs Address.
Data bus D15 to D0 100 to 96,
11 to 1
100, 99,
14 to 1
Input/
output
Used as the bidirectional data bus.
Bus control CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
87
88
89
90
92
93
94
95
90
91
92
93
95
96
97
98
Output Select signals for areas 7 to 0.
AS 69 72 Output When this pin is low, it indicates valid address
output on the address bus.
RD 70 73 Output When this pin is low, it indicates that the external
address space is being read.
HWR 71 74 Output Strobe signal: Writes to the external address bus
to indicate valid data on the upper data bus (D15
to D8).