Datasheet

Section 1 Overview
Rev. 6.00 Mar. 18, 2010 Page 46 of 982
REJ09B0054-0600
Pin No.
Type Symbol
TFP-100B
TFP-100BV
FP-100B
FP-100BV
FP-100A
FP-100AV I/O Function
Data bus D15 to
D0
100 to 96,
11 to 1
100, 99,
14 to 1
Input/
output
Used as the bidirectional data bus.
Bus
control
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
87
88
89
90
92
93
94
95
90
91
92
93
95
96
97
98
Output Select signals for areas 7 to 0.
AS 69 72 Output When this pin is low, it indicates valid
address output on the address bus.
RD 70 73 Output When this pin is low, it indicates that the
external address space is being read.
HWR 71 74 Output Strobe signal: Writes to the external
address bus to indicate valid data on the
upper data bus (D15 to D8).
LWR 72 75 Output Strobe signal: Writes to the external bus to
indicate valid data on the lower data bus
(D7 to D0).
WAIT 73 76 Input Requests insertion of wait states in bus
cycle when accesses to the external three-
state address.
16-bit timer-
pulse unit
(TPU)
TCLKD
TCLKC
TCLKB
TCLKA
41
39
37
36
44
42
40
39
Input These pins input an external clock.
TIOCA0
TIOCB0
TIOCC0
TIOCD0
34
35
36
37
37
38
39
40
Input/
Output
Pins for the TGRA_0 to TGRD_0 input
capture input, output compare output, or
PWM output.
TIOCA1
TIOCB1
38
39
41
42
Input/
Output
Pins for the TGRA_1 and TGRB_1 input
capture input, output compare output, or
PWM output.
TIOCA2
TIOCB2
40
41
43
44
Input/
Output
Pins for the TGRA_2 and TGRB_2 input
capture input, output compare output, or
PWM output.