Datasheet

Appendix A I/O Port States in Each Pin State
Rev. 6.00 Mar. 18, 2010 Page 967 of 982
REJ09B0054-0600
Port Name
Pin Name
MCU
Operating
Mode
Power-On
Reset
Manual
Reset
Hardware
Standby
Mode
Software
Standby
Mode,
Watch Mode
Bus
Mastership
Release
State
Program
Execution
State,
Sleep Mode,
Subsleep
Mode
4 to 6 T keep T [BRLE = 0]
keep
[BRLE = 1]
T
T [BRLE = 0]
I/O port
[BRLE = 1]
BREQ
PF0/BREQ/
IRQ2
7 T keep T keep keep I/O port
4, 5 H
6 T
keep T [DDR ⋅ OPE
= 0]
T
[DDR ⋅ OPE
= 1]
H
T [DDR = 0]
I/O port
[DDR = 1]
CS0
(H in sleep
mode and
subsleep
mode.)
PG4/CS0
7 T keep T keep keep I/O port
4 to 6 T keep T [DDR ⋅ OPE
= 0]
T
[DDR ⋅ OPE
= 1]
H
T [DDR = 0]
Input port
[DDR = 1]
CS1 to CS3
PG3/CS1
PG2/CS2
PG1/CS3/
IRQ7
7 T keep T keep keep I/O port
PG0/IRQ6 4 to 7 T keep T keep keep I/O port
Legend:
H: High level
L: Low level
T: High-impedance
keep: The input port becomes high-impedance, and the output port retains its state
DDR: Data direction register
OPE: Output port enable
WAITE: Wait input enable
BRLE: Bus release enable
Notes: 1. The port state is L (address input) in modes 4 and 5.
2. Not available in the H8S/2237 Group and H8S/2227 Group.
3. Supported only by the H8S/2239 Group.
4. Not available in the H8S/2227 Group.