Datasheet

Appendix A I/O Port States in Each Pin State
Rev. 6.00 Mar. 18, 2010 Page 966 of 982
REJ09B0054-0600
Port Name
Pin Name
MCU
Operating
Mode
Power-On
Reset
Manual
Reset
Hardware
Standby
Mode
Software
Standby
Mode,
Watch Mode
Bus
Mastership
Release
State
Program
Execution
State,
Sleep Mode,
Subsleep
Mode
4 to 6 Clock
output
[DDR = 0]
Input port
[DDR = 1]
Clock
output
T [DDR = 0]
Input port
[DDR = 1]
H
[DDR = 0]
Input port
[DDR = 1]
Clock output
[DDR = 0]
Input port
[DDR = 1]
Clock output
PF7/φ
7 T keep T [DDR = 0]
Input port
[DDR = 1]
H
[DDR = 0]
Input port
[DDR = 1]
Clock output
[DDR = 0]
Input port
[DDR = 1]
Clock output
4 to 6 H H T [OPE= 0]
T
[OPE= 1]
H
T AS, RD, HWR PF6/AS
PF5/RD
PF4/HWR
7 T keep T keep keep I/O port
PF3/LWR/
ADTRG/IRQ3
7 T keep T keep keep I/O port
8-bit bus 4 to 6 keep T keep keep I/O port
16-bit
bus
4 to 6
(Mode 4)
H
(Mode 5,
6)
T
H T [OPE = 0]
T
[OPE = 1]
H
T LWR
4 to 6 T keep T [WAITE = 0]
keep
[WAITE = 1]
T
[WAITE = 0]
keep
[WAITE = 1]
T
[WAITE = 0]
I/O port
[WAITE = 1]
WAIT
PF2/WAIT
7 T keep T keep keep I/O port
PF1/BACK/
BUZZ
4 to 6 T keep T [BRLE = 0]
keep
[BRLE = 1]
H
L [BRLE = 0]
I/O port
[BRLE = 1]
BACK
7 T keep T keep keep I/O port