Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 957 of 982
REJ09B0054-0600
t
TED
T
2
or T
3
T
1
φ
TEND1, TEND0
t
TED
Figure 27.22 DMAC TEND Output Timing
t
DRQH
t
DRQS
φ
DREQ1, DREQ0
Figure 27.23 DMAC DREQ Input Timing
27.7.4 Timing of On-Chip Peripheral Modules
Figures 27.24 to 27.34 show the timing of on-chip peripheral modules.
t
PRS
T
1
T
2
t
PWD
t
PRH
φ
Ports 1, 3, 4, 7, 9,
A to G (read)
Ports 1, 3, 7,
A to G (write)
Figure 27.24 I/O Port Input/Output Timing