Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 954 of 982
REJ09B0054-0600
t
AD
t
ACC1
t
RDS
t
RDH
T
1
T
2
or T
3
T
1
t
RSD2
φ
CS0
AS
A23 to A0
RD
(read)
D15 to D0
(read)
Figure 27.18 Burst ROM Access Timing (One-State Access)
BREQ
BACK
t
BACD
t
BZD
A23 to A0,
CS7 to CS0,
AS, RD,
HWR, LWR
t
BACD
t
BZD
t
BRQS
t
BRQS
φ
Figure 27.19 External Bus Release Timing