To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 5. Contents 6. Overview 7.
Preface The H8S/2558 Group, H8S/2239 Group, H8S/2238 Group, H8S/2237 Group, and H8S/2227 Group are high-performance microcomputers made up of the internal 32-bit configuration H8S/2000 CPU as their cores, and the peripheral functions required to configure a system. TM A single-power flash memory (F-ZTAT *) version and masked ROM version are available for these LSIs’ ROM.
List of On-Chip Peripheral Functions: H8S/2258 Group Group Name H8S/2239 Group H8S/2238 Group H8S/2237 Group H8S/2227 Group H8S/2237 H8S/2235 H8S/2233 H8S/2227 H8S/2225 H8S/2224 H8S/2223 Microcomputer H8S/2258 H8S/2256 H8S/2239 H8S/2238B H8S/2238R H8S/2236B H8S/2236R Bus controller (BSC) O (16 bits) O (16 bits) O (16 bits) O (16bits) O (16 bits) Data transfer controller (DTC) O O O O O DMA controller (DMAC) ⎯ O ⎯ ⎯ ⎯ PC break controller (PBC) ×2 ×2 ×2 ×2 ×2 16-bit timer pu
Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into descriptions on the CPU, system control functions, peripheral functions, and electrical characteristics. • In order to understand the details of the CPU’s functions Read the H8S/2600 Series, H8S/2000 Series Software Manual.
User's Manuals for Development Tools: Document Title Document No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual REJ10J2039 High-performance Embedded Workshop User's Manual REJ10J2037 Application Notes: Document Title Document No. H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464 Rev. 6.00 Mar.
Main Revisions for This Edition Item Page Revision (See Manual for Details) 1.3.2 Pin Arrangements in Each Mode 20 to 23 Table amended Pin Name Table 1.1 Pin Arrangements in Each Mode of H8S/2258 Group Mode 4 23 Mode 5 Mode 6 Flash Memory Programmable Mode* Mode 7 Note added Note: * The NC should be left open. Table 1.2 Pin Arrangements 24 to 28 Table amended in Each Mode of H8S/2239 Pin No.
Item Page Revision (See Manual for Details) 2.3 Address Space 70 Figure amended H'00000000 Figure 2.5 Memory Map 16 Mbytes H'00FFFFFF Program area Data area Not available in this LSI H'FFFFFFFF (b) Advanced Mode 2.6 Instruction Set 79 Table 2.1 Instruction Classification Table amended Function Instructions Size Types Data transfer MOV POP*1, PUSH*1 B/W/L 5 LDM*5, STM*5 L W/L Note added Notes: 5. Only register ER0 to ER6 should be used when using the STM/LDM instruction. 2.6.
Item Page Revision (See Manual for Details) 4.8 Usage Note 126 Figure amended Figure 4.3 Operation When SP Value Is Odd CCR SP R1L SP H'FFFEFA H'FFFEFB PC PC H'FFFEFC H'FFFEFD SP H'FFFEFF TRAPA instruction executed SP set to H'FFFEFF 5.6.5 IRQ Interrupt 156 5.6.5 added 5.6.6 NMI Interrupts Usage 156 Notes 5.6.6 added 6.3.4 Operation in Transitions to Power-Down Modes 161 Description amended 7.6.
Item Page 10.2.2 Port 3 Data Register 316 (P3DR) Revision (See Manual for Details) Table amended Bit Bit Name Initial Value R/W Description 7 — Undefined — Reserved 6 P36DR 0 R/W 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W These bits are always read as undefined value. 10.4.2 Port 7 Data Register 323 (P7DR) 10.6.
Item Page 10.9.2 Port D Data Register 344 (PDDR) 10.10.2 Port E Data Register (PEDR) 347 10.11.2 Port F Data Register 351 (PFDR) 10.12.2 Port G Data Register (PGDR) 355 Revision (See Manual for Details) Table amended Bit Bit Name Initial Value R/W Description 7 PD7DR 0 R/W 6 PD6DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port.
Item Page Revision (See Manual for Details) 11.3.1 Timer Control Register (TCR) 367 Table amended Bit Bit Name Initial Value R/W Description 4 3 CKEG1 CKEG0 0 0 R/W R/W Clock Edge 1 and 0 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4*, and 5*, this setting is ignored and the phase counting mode setting has priority.
Item 2 16.3.6 I C Bus Control Register (ICCR) Page Revision (See Manual for Details) 644 Table amended Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I2C Bus Interface Enable When this bit is set to 1, the I2C bus interface module is enabled to send/receive data and drive the bus since it is connected to the SCL and SDA pins. ICMR and ICDR can be accessed. SCL and SDA output is disabled (and input to SCL and SDA is enabled) when this bit is cleared to 0. SAR and SARX can be accessed.
Item Page Revision (See Manual for Details) 16.6 Usage Notes 681 Figure amended Start condition (retransmission) Figure 16.22 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission SCL 9 SDA ACK Bit 7 Data output IRIC [5] ICDR write (next transmit data) [4] IRIC determination [3] (Restart) Start condition instruction issuance [2] Detemination of SCL = Low [1] IRIC determination Figure 16.
Item Page Revision (See Manual for Details) 705 17.8.4 Range of Analog Power Supply and Other Pin Settings • 27.3.2 DC Characteristics Table amended 865 Table 27.14 DC Characteristics (1) Description added Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open.
Item Page Revision (See Manual for Details) 27.5.2 DC Characteristics 909 Note added Notes: 5. When VCC < AVCC, the maximum value for P40 and P41 is VCC + 0.3 V. Table 27.39 DC Characteristics (1) 27.5.4 A/D Conversion Characteristics 923 Table condition amended Condition A (F-ZTAT version and masked ROM version): Table 27.47 A/D Conversion Characteristics VCC = 2.7 V to 3.6 V*, AVCC = 2.7 V to 3.6 V*, Vref = 2.7 V to AVCC, VSS =AVSS = 0 V, φ = 2 to 13.
Item Page Revision (See Manual for Details) 27.6.4 A/D Conversion Characteristics 944 Table condition amended Table 27.57 A/D Conversion Characteristics Condition A (ZTAT version): VCC = 2.7 V to 3.6 V*, AVCC = 2.7 V to 3.6 V*, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version, Masked ROM version): VCC = 2.7 V to 3.6 V*, AVCC = 2.7 V to 3.6 V*, Vref = 2.
Item Page Appendix B Product Codes 971 Revision (See Manual for Details) Table amended Package Table B.3 Product Codes of H8S/2238 Group Product Type H8S/2236B Masked 5-V version (Package Code) Product Code Mark Code HD6432236B HD6432236B(***)TE 100-pin TQFP (TFP-100B) HD6432236B(***)TF 100-pin TQFP (TFP-100G) HD6432236B(***)F 100-pin QFP (FP-100A) ROM version 2 On-chip I C HD6432236BW bus interface product (5-V version) H8S/2236R Masked 3-V version, ROM 2.
Contents Section 1 Overview............................................................................................. 1 1.1 1.2 1.3 Features ............................................................................................................................... 1 Internal Block Diagram....................................................................................................... 4 Pin Description..............................................................................................
2.8 2.9 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)......................................92 2.7.8 Memory Indirect—@@aa:8 ..................................................................................93 2.7.9 Effective Address Calculation ...............................................................................94 Processing States.................................................................................................................96 Usage Notes .............................
5.3 5.4 5.5 5.6 Register Descriptions ........................................................................................................129 5.3.1 Interrupt Priority Registers A to L, and O (IPRA to IPRL, IPRO) ......................130 5.3.2 IRQ Enable Register (IER) ..................................................................................131 5.3.3 IRQ Sense Control Registers H and L (ISCRH and ISCRL) ...............................131 5.3.4 IRQ Status Register (ISR)......................
6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 CMFA and CMFB ............................................................................................... 163 PC Break Interrupt when DTC and DMAC Is Bus Master .................................. 163 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, and RTS Instruction..................................................................... 163 I Bit Set by LDC, ANDC, ORC, and XORC Instruction.....................................
7.10.1 Operation .............................................................................................................199 7.10.2 Bus Transfer Timing ............................................................................................200 7.10.3 External Bus Release Usage Note........................................................................200 7.11 Resets and the Bus Controller ...........................................................................................
8.7.3 8.7.4 8.7.5 8.7.6 8.7.7 Medium-Speed Mode........................................................................................... 277 Activation by Falling Edge on DREQ Pin ........................................................... 278 Activation Source Acceptance............................................................................. 278 Internal Interrupt after End of Transfer................................................................ 278 Channel Re-Setting ...........................
10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.1.1 Port 1 Data Direction Register (P1DDR).............................................................309 10.1.2 Port 1 Data Register (P1DR)................................................................................310 10.1.3 Port 1 Register (PORT1)......................................................................................310 10.1.4 Pin Functions .....................................................................................................
10.9 10.10 10.11 10.12 10.13 10.8.4 Port C Pull-Up MOS Control Register (PCPCR) ................................................ 341 10.8.5 Pin Functions ....................................................................................................... 342 10.8.6 Input Pull-Up MOS States in Port C.................................................................... 342 Port D.............................................................................................................................
11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.3.8 Timer Start Register (TSTR)................................................................................396 11.3.9 Timer Synchronous Register (TSYR) ..................................................................397 Operation...........................................................................................................................398 11.4.1 Basic Functions......................................................................................
12.3.5 Timer Control/Status Register (TCSR)................................................................ 447 12.4 Operation .......................................................................................................................... 452 12.4.1 Pulse Output......................................................................................................... 452 12.5 Operation Timing............................................................................................................
13.6.2 13.6.3 13.6.4 13.6.5 13.6.6 13.6.7 Contention between Timer Counter (TCNT) Write and Increment .....................478 Changing Value of PSS or CKS2 to CKS0..........................................................479 Switching between Watchdog Timer Mode and Interval Timer Mode................479 Internal Reset in Watchdog Timer Mode.............................................................479 OVF Flag Clearing in Interval Timer Mode ........................................................
14.4.2 Slave Receive Operation...................................................................................... 529 14.4.3 Master Reception ................................................................................................. 533 14.4.4 Slave Transmission .............................................................................................. 536 14.5 Interrupt Sources...............................................................................................................
15.5.2 Multiprocessor Serial Data Reception..................................................................599 15.6 Operation in Clocked Synchronous Mode ........................................................................602 15.6.1 Clock....................................................................................................................602 15.6.2 SCI Initialization (Clocked Synchronous Mode) .................................................602 15.6.
16.3.5 Serial Control Register X (SCRX)....................................................................... 643 2 16.3.6 I C Bus Control Register (ICCR) ......................................................................... 644 2 16.3.7 I C Bus Status Register (ICSR)............................................................................ 649 16.3.8 DDC Switch Register (DDCSWR) ...................................................................... 653 16.4 Operation ................................
17.8.6 Notes on Noise Countermeasures ........................................................................705 Section 18 D/A Converter................................................................................. 707 18.1 Features .............................................................................................................................707 18.2 Input/Output Pins .............................................................................................................. 708 18.
20.11 20.12 20.13 20.14 Programmer Mode ............................................................................................................ 743 Power-Down States for Flash Memory............................................................................. 745 Flash Memory Programming and Erasing Precautions..................................................... 745 Note on Switching from F-ZTAT Version to Masked ROM Version .............................. 751 Section 21 Masked ROM ..................
24.2 Medium-Speed Mode........................................................................................................790 24.3 Sleep Mode .......................................................................................................................791 24.3.1 Transition to Sleep Mode.....................................................................................791 24.3.2 Exiting Sleep Mode..............................................................................................
25.3 Power Supply Connection for H8S/2239 Group, H8S/2238R, H8S/2236R, H8S/2237 Group, and H8S/2227 Group (No Internal Power Supply Step-Down Circuit) ................ 804 25.4 Note on Bypass Capacitor................................................................................................. 805 Section 26 List of Registers...............................................................................807 26.1 Register Addresses (In Address Order).......................................................
27.6.1 Absolute Maximum Ratings ................................................................................927 27.6.2 DC Characteristics ...............................................................................................928 27.6.3 AC Characteristics ...............................................................................................937 27.6.4 A/D Conversion Characteristics...........................................................................944 27.6.
Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2258 Group ......................................................... 4 Figure 1.2 Internal Block Diagram of H8S/2239 Group ......................................................... 5 Figure 1.3 Internal Block Diagram of H8S/2238 Group ......................................................... 6 Figure 1.4 Internal Block Diagram of H8S/2237 Group ......................................................... 7 Figure 1.
Figure 2.9 Figure 2.10 Figure 2.11 Figure 2.12 Figure 2.13 Figure 2.14 General Register Data Formats (2)......................................................................... 77 Memory Data Formats ........................................................................................... 78 Instruction Formats (Examples) ............................................................................. 90 Branch Address Specification in Memory Indirect Mode......................................
Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6 Figure 7.7 Figure 7.8 Figure 7.9 Figure 7.10 Figure 7.11 Figure 7.12 Figure 7.13 Figure 7.14 Figure 7.15 Figure 7.16 Figure 7.17 Figure 7.18 Figure 7.19 Figure 7.20 Figure 7.21 Figure 7.22 Figure 7.23 Figure 7.24 Overview of Area Divisions................................................................................. 175 CSn Signal Output Timing (n = 0 to 7) ................................................................
Figure 8.15 Figure 8.16 Figure 8.17 Figure 8.18 Figure 8.19 Figure 8.20 Figure 8.21 Figure 8.22 Figure 8.23 Figure 8.24 Figure 8.25 Figure 8.26 Figure 8.27 Figure 8.28 Figure 8.29 Figure 8.30 Figure 8.31 Figure 8.32 Figure 8.33 Figure 8.34 Figure 8.35 Figure 8.36 Figure 8.37 Figure 8.38 Figure 8.39 Operation in Block Transfer Mode (BLKDIR = 1)..............................................253 Operation Flow in Block Transfer Mode .............................................................
Figure 9.12 DTC Operation Timing (Example of Chain Transfer) ......................................... 299 Section 10 I/O Ports Figure 10.1 Types of Open Drain Outputs .............................................................................. 318 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.1 Block Diagram of TPU (H8S/2258 Group, H8S/2239 Group, H8S/2238 Group, and H8S/2237 Group) .......................................................................................... 362 Figure 11.
Figure 11.34 Figure 11.35 Figure 11.36 Figure 11.37 Figure 11.38 Figure 11.39 Figure 11.40 Figure 11.41 Figure 11.42 Figure 11.43 Figure 11.44 Figure 11.45 Figure 11.46 Figure 11.47 Figure 11.48 Figure 11.49 Figure 11.50 Figure 11.51 Figure 11.52 Figure 11.53 Figure 11.54 Input Capture Input Signal Timing ......................................................................428 Counter Clear Timing (Compare Match) .............................................................
Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Interval Timer Mode Operation ........................................................................... 475 Timing of OVF Setting ........................................................................................ 475 Timing of WOVF Setting..................................................................................... 476 Writing to TCNT, TCSR.................................................................................
Figure 15.10 Sample Serial Transmission Flowchart ................................................................591 Figure 15.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) .................................................592 Figure 15.12 Sample Serial Reception Data Flowchart (1) .......................................................594 Figure 15.12 Sample Serial Reception Data Flowchart (2) .......................................................595 Figure 15.
Figure 15.44 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output)........................................................ 631 2 Section 16 I C Bus Interface (IIC) (Option) 2 Figure 16.1 Block Diagram of I C Bus Interface..................................................................... 635 2 Figure 16.2 I C Bus Interface Connections (Example: This LSI as Master) ........................... 636 2 2 Figure 16.
Section 17 A/D Converter Figure 17.1 Block Diagram of A/D Converter ........................................................................690 Figure 17.2 Access to ADDR (When Reading H'AA40) ........................................................696 Figure 17.3 Example of A/D converter Operation (Single Mode, Channel 1 Selected)..........698 Figure 17.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) ....................................................699 Figure 17.
Section 22 PROM Figure 22.1 HD6472237 Socket Adapter Pin Correspondence Diagram (FP-100B, TFP-100B, TFP-100G)....................................................................... 756 Figure 22.2 HD6472237 Socket Adapter Pin Correspondence Diagram (FP-100A) .............. 757 Figure 22.3 Memory Map in PROM Mode ............................................................................. 758 Figure 22.4 High-Speed Programming Flowchart...................................................................
Figure 27.5 Figure 27.6 Figure 27.7 Figure 27.8 Figure 27.9 Figure 27.10 Figure 27.11 Figure 27.12 Figure 27.13 Figure 27.14 Figure 27.15 Figure 27.16 Figure 27.17 Figure 27.18 Figure 27.19 Figure 27.20 Figure 27.21 Figure 27.22 Figure 27.23 Figure 27.24 Figure 27.25 Figure 27.26 Figure 27.27 Figure 27.28 Figure 27.29 Figure 27.30 Figure 27.31 Figure 27.32 Figure 27.33 Figure 27.34 Power Supply Voltage and Operating Ranges (H8S/2237 Group and H8S/2227 Group).................................................
Tables Section 1 Overview Table 1.1 Pin Arrangements in Each Mode of H8S/2258 Group ........................................... 20 Table 1.2 Pin Arrangements in Each Mode of H8S/2239 Group ........................................... 24 Table 1.3 Pin Arrangements in Each Mode of H8S/2238 Group ........................................... 29 Table 1.4 Pin Arrangements in Each Mode of H8S/2237 Group ........................................... 34 Table 1.5 Pin Arrangements in Each Mode of H8S/2227 Group ........
Section 5 Interrupt Controller Table 5.1 Pin Configuration ...................................................................................................129 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................137 Table 5.3 Interrupt Control Modes.........................................................................................142 Table 5.4 Interrupts Selected in Each Interrupt Control Mode (1) .........................................
Table 9.7 Number of States Required for Each Execution Status .......................................... 300 Section 10 I/O Ports Table 10.1 Port Functions ........................................................................................................ 306 Table 10.2 Input Pull-Up MOS States in Port A ...................................................................... 332 Table 10.3 Input Pull-Up MOS States in Port B ......................................................................
Table 11.29 Table 11.30 Table 11.31 Table 11.32 Table 11.33 Table 11.34 Table 11.35 Table 11.36 Cascaded Combinations .........................................................................................409 PWM Output Registers and Output Pins................................................................412 Clock Input Pins in Phase Counting Mode.............................................................416 Up/Down-Count Conditions in Phase Counting Mode 1 .......................................
Table 15.10 Table 15.11 Table 15.12 Table 15.13 Serial Transfer Formats (Asynchronous Mode) ..................................................... 586 SSR Status Flags and Receive Data Handling........................................................ 593 Interrupt Sources of Serial Communication Interface Mode.................................. 623 Interrupt Sources in Smart Card Interface Mode.................................................... 624 2 Section 16 I C Bus Interface (IIC) (Option) Table 16.
Table 22.2 Table 22.3 Table 22.4 Table 22.5 Socket Adapters......................................................................................................758 Mode Selection in PROM Mode ............................................................................759 DC Characteristics in PROM Mode .......................................................................761 AC Characteristics in PROM Mode .......................................................................
Table 27.8 Table 27.9 Table 27.10 Table 27.11 Table 27.12 Table 27.13 Table 27.14 Table 27.14 Table 27.14 Table 27.15 Table 27.16 Table 27.17 Table 27.18 Table 27.19 Table 27.20 Table 27.21 Table 27.22 Table 27.23 Table 27.24 Table 27.25 Table 27.26 Table 27.27 Table 27.27 Table 27.27 Table 27.28 Table 27.29 Table 27.30 Table 27.31 Table 27.32 Table 27.33 Table 27.34 Table 27.35 Table 27.36 Table 27.37 Table 27.38 Table 27.39 Table 27.39 Table 27.39 Table 27.40 Table 27.
Table 27.42 Table 27.43 Table 27.44 Table 27.45 Table 27.46 Table 27.47 Table 27.48 Table 27.49 Table 27.50 Table 27.51 Table 27.51 Table 27.51 Table 27.51 Table 27.52 Table 27.53 Table 27.54 Table 27.55 Table 27.56 Table 27.57 Table 27.58 Table 27.59 Clock Timing..........................................................................................................916 Control Signal Timing............................................................................................917 Bus Timing..........
Rev. 6.00 Mar.
Section 1 Overview Section 1 Overview 1.1 Features • High-speed H8S/2000 central processing unit with an internal 16-bit architecture ⎯ Upward-compatible with H8/300 and H8/300H CPUs on an object level ⎯ Sixteen 16-bit general registers ⎯ 65 basic instructions • Various peripheral functions ⎯ PC break controller ⎯ DMA controller (DMAC) Supported only by the H8S/2239 Group.
Section 1 Overview • On-chip memory ROM Model ROM RAM Flash memory version HD64F2258 256 kbytes 16 kbytes HD64F2239 384 kbytes 32 kbytes HD64F2238B 256 kbytes 16 kbytes HD64F2238R 256 kbytes 16 kbytes HD64F2227 128 kbytes 16 kbytes PROM version HD6472237 128 kbytes 16 kbytes Masked ROM version HD6432258 256 kbytes 16 kbytes HD6432258W 256 kbytes 16 kbytes HD6432256 128 kbytes 8 kbytes HD6432256W 128 kbytes 8 kbytes HD6432239 384 kbytes 32 kbytes HD6432239W 384 kbyte
Section 1 Overview • Compact package Package (Code)* TQFP-100 6 Body Size Pin Pitch TFP-100B, TFP-100BV 14.0 × 14.0 mm 0.5 mm TQFP-100* TFP-100G, TFP-100GV 12.0 × 12.0 mm 0.4 mm QFP-100* 3 QFP-100* FP-100A, FP-100AV 14.0 × 20.0 mm 0.65 mm FP-100B, FP-100BV 14.0 × 14.0 mm 0.5 mm 4 LFBGA-112* BP-112, BP-112V 10.0 × 10.0 mm 0.8 mm 5 TFBGA-112* TBP-112A, TBP-112AV 10.0 × 10.0 mm 0.8 mm 1 2 Notes: 1. Not supported by the H8S/2258 Group. 2.
Section 1 Overview 1.
Port A Port B 8-bit timer (4 channels) ROM Port F PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 Port C WDT1 (subclock) WDT0 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 Port 3 PC break controller (2 channels) PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 P36 P35/SCK1/SCL0/IRQ5 P34/RxD1/SDA0 P33/TxD1/SCL1 P32/SCK0/SDA1/IRQ4 P31/Rx
Port A Port B 8-bit timer (4 channels) ROM Port F PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 WDT1 (subclock) Port C WDT0 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 Port 3 PC break controller (2 channels) PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 P36 P35/SCK1/SCL0/IRQ5 P34/RxD1/SDA0 P33/TxD1/SCL1 P32/SCK0/SDA1/IRQ4 P31/Rx
Port A Port B PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P36 P35/SCK1/IRQ5 P34/RxD1 P33/TxD1 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0 P97/DA1 P96/DA0 ROM 8-bit timer (2 channels) Port F PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 WDT1 (subclock) Port C WDT0 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 Port 3 PC break controller (2 channels) PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2
Port A Port B PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P36 P35/SCK1/IRQ5 P34/RxD1 P33/TxD1 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0 P97 P96 ROM Port F 8-bit timer (2 channels) SCI (3 channels) RAM TPU (3 channels) Port 4 P47 / AN7 P46 / AN6 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 Port 7 Vref AVCC AVSS Port 1 P70 / T M R I 0 1 /TMCI01/CS4 P71 / CS5 P72 / TMO0/ CS6 P73 / TMO1/ CS7 P74 / MRES P75 / SCK3 P76 / RxD3 P77 / TxD3 A/D converter (8 channels) P10 / TIOCA0 /A20 P1
Section 1 Overview 1.3 Pin Description 1.3.
FP-100A FP-100AV (TOP VIEW) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 PD6/D14 PD7/D15 CVCC PC0/A0 VSS PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8/TIOCA3 PB1/A9/TIOCB3 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 P32/SCK0/SDA1/IRQ4 P
Section 1 Overview (2) Pin Arrangement of H8S/2239 Group TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100BV (TOP VIEW) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P96/DA0 P97/DA1 AVSS P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0
Section 1 Overview A NC 11 (Reserve) B C D E F G H J K L PF1/ BACK/ BUZZ PF4/ HWR PF7/φ EXTAL XTAL STBY OSC1 MD0 P40/AN0 NC (Reserve) NC (Reserve) PF2/ WAIT PF5/RD FWE VSS VCC OSC2 AVCC P41/AN1 P42/AN2 PF0/ BREQ/ IRQ2 PF3/ LWR/ ADTRG/ IRQ3 MD2 VCC NMI MD1 NC (Reserve) P43/AN3 P45/AN5 P34/ RxD1/ SDA0 P31/ RxD0 PF6/AS VSS RES Vref P44/AN4 P46/AN6 P96/DA0 P76/ RxD3 P77/ TxD3 P47/AN7 P97/DA1 AVSS AVSS P17/ TIOCB2/ TCLKD P14/ TIOCA1/ IRQ0 P16/ TIOCA2/ IRQ1
Section 1 Overview (3) Pin Arrangement of H8S/2238 Group TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100BV (TOP VIEW) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P96/DA0 P97/DA1 AVSS P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0
FP-100A FP-100AV (TOP VIEW) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P45/AN5 P46/AN6 P47/AN7 P96/DA0 P97/DA1 AVSS P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA/A22 P11/TIOCB0/A21 P10/TIOCA0/A20 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PE2/D2 PE3/D3 PE4
Section 1 Overview A B C D E F G H J K L 11 NC PF1/ BACK/ BUZZ PF4/ HWR PF7/φ EXTAL XTAL STBY OSC1 MD0 P40/AN0 NC 10 P30/ TxD0 NC PF2/ WAIT PF5/RD FWE VSS VCC OSC2 9 P33/ TxD1/ SCL1 PF3/L PF0/ WR/ BREQ/ ADTRG/ IRQ2 IRQ3 MD2 VCC NMI MD1 8 P36 PF6/AS VSS RES Vref 7 P75/ TMO3/ SCK3 6 P32/ SCK0/ SDA1/ IRQ4 P35/ SCK1/ SCL0/ IRQ5 P34/ RxD1/ SDA0 P31/ RxD0 P74/ P76/ P77/ TMO2/ RxD3 TxD3 MRES P70/ P71/ P72/ TMRI23/ P73/ TMRI01/ TMO0/ TMCI23/ TMO1/ TMCI01/ CS7 CS6 CS
Section 1 Overview (4) Pin Arrangement of H8S/2237 Group TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100BV (TOP VIEW) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P96/DA0 P97/DA1 AVSS P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0
FP-100A FP-100AV (TOP VIEW) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P45/AN5 P46/AN6 P47/AN7 P96/DA0 P97/DA1 AVSS P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA/A22 P11/TIOCB0/A21 P10/TIOCA0/A20 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PE2/D2 PE3/D3 PE4
Section 1 Overview (5) Pin Arrangement of H8S/2227 Group TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B* FP-100BV* (TOP VIEW) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P96 P97 AVSS P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA
FP-100A FP-100AV (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P45/AN5 P46/AN6 P47/AN7 P96 P97 AVSS P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA/A22 P11/TIOCB0/A21 P10/TIOCA0/A20 PA3/A19 PA2/A18 PA1/A17 PA0/A16 PB7/A15 PB6/A14 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 PD0/D8 PD1/D
Section 1 Overview 1.3.2 Pin Arrangements in Each Mode Tables 1.1 to 1.5 show the pin arrangements in each mode. Table 1.1 Pin Arrangements in Each Mode of H8S/2258 Group Pin No.
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Section 1 Overview Table 1.2 Pin Arrangements in Each Mode of H8S/2239 Group Pin No.
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Section 1 Overview Pin No. Pin Name TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B TBP-112A*1 FP-100BV TBP-112AV*1 Mode 4 Mode 5 Mode 6 Mode 7 Flash Memory Programmable Mode*2 98 C4 PE2/D2 PE2/D2 PE2/D2 PE2 NC 99 B3 PE3/D3 PE3/D3 PE3/D3 PE3 VCC 100 A2 PE4/D4 PE4/D4 PE4/D4 PE4 VSS Notes: 1. Supported only by HD64F2239. 2. The NC should be left open. Rev. 6.00 Mar.
Section 1 Overview Table 1.3 Pin Arrangements in Each Mode of H8S/2238 Group Pin No.
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Section 1 Overview Table 1.4 Pin Arrangements in Each Mode of H8S/2237 Group Pin No.
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Section 1 Overview Table 1.5 Pin Arrangements in Each Mode of H8S/2227 Group Pin No.
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Section 1 Overview 1.3.3 Pin Functions Table 1.6 lists the pin functions of the H8S/2258 Group. Table 1.7 lists the pin functions of the H8S/2239 Group and H8S/2238 Group. Table 1.8 lists the pin functions of the H8S/2237 Group and H8S/2227 Group. Table 1.6 Pin Functions of H8S/2258 Group Pin No. Type Symbol TFP-100B TFP-100BV FP-100B FP-100BV Power supply VCC 62 65 Input For connection to the power supply. Connect all VCC pins to the system power supply. CVCC 12 15 Input Connect a 0.
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV FP-100B FP-100BV Clock OSC2 57 60 Input Connects to a 32.768 kHz crystal resonator. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal resonator. φ 68 71 Output Supplies the system clock to external devices. Operating mode control MD2 MD1 MD0 67 56 55 70 59 58 Input Sets the operating mode. Inputs at these pins should not be changed during operation.
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV FP-100B FP-100BV Data bus D15 to D0 100 to 96, 11 to 1 100, 99, 14 to 1 Input/ output Used as the bidirectional data bus. Bus control CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 87 88 89 90 92 93 94 95 90 91 92 93 95 96 97 98 Output Select signals for areas 7 to 0. AS 69 72 Output When this pin is low, it indicates valid address output on the address bus.
Section 1 Overview Pin No. TFP-100B TFP-100BV FP-100B FP-100BV FP-100A FP-100AV 16-bit timer- TIOCA3 pulse unit TIOCB3 (TPU) TIOCC3 TIOCD3 22 23 24 25 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Type I/O Function 25 26 27 28 Input/ Output Pins for the TGRA_3 to TGRD_3 input capture input, output compare output, or PWM output. 26 27 29 30 Input/ Output Pins for the TGRA_4 and TGRB_4 input capture input, output compare output, or PWM output.
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV FP-100B FP-100BV IEBus controller (IEB) Tx 93 96 Output IEB transmit data output pin. Rx 94 97 Input IEB receive data input pin A/D converter AN7 to AN0 52 to 45 55 to 48 Input Analog input pins for the A/D converter. ADTRG 72 75 Input Pin for input of an external trigger to start A/D conversion. D/A converter DA1 DA0 43 44 46 47 Output Analog output pins for the D/A converter.
Section 1 Overview Pin No. TFP-100B TFP-100BV FP-100B FP-100BV FP-100A FP-100AV Type Symbol I/O ports PC7 to PC0 21 to 15, 13 PD7 to PD0 11 to 4 PE7 to PE0 Note: * I/O Function 24 to 18, 16 Input/ Output 8-bit I/O pins. 14 to 7 Input/ Output 8-bit I/O pins. 100 to 96, 3 to 1 100, 99, 6 to 1 Input/ Output 8-bit I/O pins. PF7 to PF0 75 to 68 78 to 71 Input/ Output 8-bit I/O pins. PG4 to PG0 95 to 91 98 to 94 Input/ Output 5-bit I/O pins.
Section 1 Overview Table 1.7 Pin Functions of H8S/2239 Group and H8S/2238 Group Pin No. Type Symbol TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A*3 FP-100BV FP-100AV*3 Power supply VCC 62 65 F9, G10 Input For connection to the power supply. Connect all VCC pins to the system power supply. CVCC 12 15 E2, F3 Input With a 5-V external power supply (H8S/2238B used), connect a 0.1-µF stabilization capacitance between this pin and ground.
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A*3 FP-100BV FP-100AV*3 Clock OSC2 57 60 H10 Input Connects to a 32.768 kHz crystal resonator. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal resonator. φ 68 71 D11 Output Supplies the system clock to external devices. Operating mode control MD2 MD1 MD0 67 56 55 70 59 58 E9 H9 J11 Input Sets the operating mode.
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A*3 FP-100BV FP-100AV*3 BP-112*1 BP-112V*1 TBP-112A*4 TBP-112AV*4 I/O Function Address bus A23 to A0 37 to 15, 13 40 to 18, 16 L5, L4, L3, Output L2, K5, K4, K3, K2, K1, J5, J4, J3, J2, J1, H5, H4, H3, H2, H1, G4, G3, G2, G1, F1 Outputs Address.
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A*3 FP-100BV FP-100AV*3 DMA controller (DMAC)*2 DREQ1 DREQ0 89 90 ⎯ B6 D6 Input Request DMAC activation. (Supported only by the H8S/2239 Group.) TEND1 TEND0 87 88 ⎯ C6 A6 Output Indicate that the DMAC has ended transmitting data. (Supported only by the H8S/2239 Group.) DACK1 DACK0 35 34 ⎯ J5 H5 Output These pins function as single address transmitting acknowledge of DMAC.
Section 1 Overview Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A*3 FP-100BV FP-100AV*3 BP-112*1 BP-112V*1 TBP-112A*4 TBP-112AV*4 I/O Function Type Symbol 8-bit timer TMO3 to 88 to 85 TMO0 91 to 88 A7, A6, B7, Output C6 Compare-match output pins. TMCI23 TMCI01 89 90 92 93 B6 D6 Input Pins for external clock input to the counter. TMRI23 TMRI01 89 90 92 93 B6 D6 Input Counter reset input pins.
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A*3 FP-100BV FP-100AV*3 D/A converter DA1 DA0 43 44 46 47 J7 L8 Output Analog output pins for the D/A converter. A/D converter, D/A converter AVCC 54 57 J10 Input Power supply pin for the A/D converter and D/A converter. If none of the A/D converter and D/A converter is used, connect this pin to the system power supply (+3 V).
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A*3 FP-100BV FP-100AV*3 I/O ports PC7 to PC0 21 to 15, 1324 to 18, 16 J1, H2, H1, Input/ G4, G3, G2, Output G1, F1 8-bit I/O pins. PD7 to PD0 11 to 4 E4, E3, E1, Input/ D3, D2, D1, Output C2, C1 8-bit I/O pins. PE7 to PE0 100 to 96, 3 100, 99, to 1 6 to 1 D4, C4, B4, Input/ B3, B2, B1, Output A3, A2 8-bit I/O pins.
Section 1 Overview Table 1.8 Pin Functions of H8S/2237 Group and H8S/2227 Group Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B*1 FP-100A*2 FP-100BV*1 FP-100AV*2 I/O Function Type Symbol Power supply VCC 12 62 15 65 Input For connection to the power supply. Connect all VCC pins to the system power supply. VSS 14 64 17 67 Input For connection to the power supply (0 V). Connect all VSS pins to the system power supply (0 V). XTAL 63 66 Input For connection to a crystal resonator.
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B*1 FP-100A*2 FP-100BV*1 FP-100AV*2 I/O System control BREQ 75 78 Input Used by an external bus master to request the bus mastership to this LSI. BACK 74 77 Output Indicates that the bus mastership has been granted to an external bus master. FEW 66 69 Input Enables/disables programming the flash memory. NMI*3 60 63 Input Nonmaskable interrupt pin. If this pin is not used, it should be fixed-high.
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B*1 FP-100A*2 FP-100BV*1 FP-100AV*2 I/O Bus control LWR 72 75 Output Strobe signal: Writes to the external bus to indicate valid data on the lower data bus (D7 to D0). WAIT 73 76 Input Requests insertion of wait states in bus cycle when accesses to the external three state address. TCLKD TCLKC TCLKB TCLKA 41 39 37 36 44 42 40 39 Input These pins input an external clock.
Section 1 Overview Pin No. Type Symbol TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B*1 FP-100A*2 FP-100BV*1 FP-100AV*2 I/O Serial communication interface (SCI)/ smart card interface TxD3 TxD2 TxD1 TxD0 83 31 79 76 86 34 82 79 Output Data output pins. (TxD2 is not available in the H8S/2227 Group.) RxD3 RxD2 RxD1 RxD0 84 32 80 77 87 35 83 80 Input Data input pins. (RxD2 is not available in the H8S/2227 Group.
Section 1 Overview Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B*1 FP-100A*2 FP-100BV*1 FP-100AV*2 I/O Function Type Symbol I/O ports P47 to P40 52 to 45 55 to 48 Input 8-bit input pins. P77 to P70 90 to 83 93 to 86 Input/ Output 8-bit I/O pins. P97 P96 43 44 46 47 Input 2-bit input pins. PA3 to PA0 33 to 30 36 to 33 Input/ Output 4-bit I/O pins. PB7 to PB0 29 to 22 32 to 25 Input/ Output 8-bit I/O pins.
Section 1 Overview Rev. 6.00 Mar.
Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.
Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ 8/16/32-bit register-register add/subtract : 1 state ⎯ 8 × 8-bit register-register multiply : 12 states ⎯ 16 ÷ 8-bit register-register divide : 12 states ⎯ 16 × 16-bit register-register multiply : 20 states ⎯ 32 ÷ 16-bit register-register divide : 20 states • Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode • Power-down state ⎯ Transition to power-down state by a SLEEP instruction ⎯ CPU cloc
Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements: • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space ⎯ Normal mode supports the same 64-kbyte address space as the H8/300 CPU. ⎯ Advanced mode supports a maximum 16-Mbyte address space.
Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode In normal mode, the exception vector table and stack have the same structure as the H8/300 CPU. • Address Space Linear access is provided to a maximum address space of 64 kbytes.
Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 Reserved*1*3 SP (SP*2 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning. Figure 2.
Section 2 CPU • Instruction Set All instructions and addressing modes can be used. • Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling.
Section 2 CPU • Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).
Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack Status 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored (When an instruction is fetched, the least significant PC bit is regarded as 0). 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Section 2 CPU Bit Bit Name Initial Value R/W Description 2 Z undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise.
Section 2 CPU 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers.
Section 2 CPU Data Type Register Number Word data Rn Data Format 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB Legend: ERn: General register ER General register E En: General register R Rn: RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 6.00 Mar.
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. 1 MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
Section 2 CPU Table 2.4 Arithmetic Operations Instructions Instruction Size* Function ADD B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.7 Bit Manipulation Instructions Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (
Section 2 CPU Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ [¬ ( of )] → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc ⎯ Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA ⎯ Starts trap-instruction exception handling. RTE ⎯ Returns from an exception-handling routine. SLEEP ⎯ Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B ⎯ if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W ⎯ if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.6.
Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA(disp) (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) 2.
Section 2 CPU 2.7.1 Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory.
Section 2 CPU To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.
Section 2 CPU 2.7.8 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode*, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long.
Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
Section 2 CPU No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
Section 2 CPU End of bus request Bus request Program execution state SLEEP instruction, SSBY = 0 tio n ha nd lin g s bu t of est d es qu En requ re s Bu or ex c tf n Re qu es eq pt r rru Inte t ues SLEEP instruction, SSBY = 1 En d o ha f ex nd ce lin pti g o Sleep mode ep Bus-released state Exception handling state RES = High, MRES = High External interrupt request Software standby mode STBY = High, RES = Low Reset state*1 Hardware standby mode*2 Power-down state*3 Notes: 1.
Section 2 CPU 2.9 Usage Notes 2.9.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.9.
Section 2 CPU The BSET, BCLR, BNOT, BST, and BIST instructions perform their operations in the following order. 1. Read the data in byte units 2. Perform the bit manipulation operation according to the instruction on the data read 3. Write the data back in byte units Example: Using the BCLR instruction to clear only bit 4 in the port 1 P1DDR register. The P1DDR register consists of 8 write-only bits and sets the I/O direction of the port 1 pins. Reading this register is invalid.
Section 2 CPU The bit manipulation operation is performed on this value that was read. In this example, bit 4 will be cleared for H'F8. P17 P16 P15 P14 P13 P12 P11 P10 Output Output Output Output Input Input Input Input P1DDR 1 1 1 1 0 0 0 0 After bit manipulation 1 1 1 0 1 0 0 0 I/O After the bit manipulation operation, this data will be written to P1DDR, and the BCLR instruction completes.
Section 2 CPU Write data to the work area Initial value write Write the work area data to the register that includes write-only bits Access the work area data (data transfer and bit manipulation instructions can be used) Modifying the value of a register that includes write-only bits Write the work area data to the register that includes write-only bits Figure 2.
Section 2 CPU To switch P14 from being an output pin to being an input pin, we must change the value of P1DDR bit 4 from 1 to 0 (H'F0 → H'E0). Here, were execute a BCLR instruction for RAM0. BCLR I/O #4, @RAM0 P17 P16 P15 P14 P13 P12 P11 P10 Output Output Output Output Input Input Input Input P1DDR 1 1 1 1 0 0 0 0 RAM0 1 1 1 0 0 0 0 0 Since RAM0 can be read and written, when the bit manipulation instruction is executed, only bit 4 in RAM0 is cleared.
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection The LSI supports four operating modes (modes 7 to 4). These operating modes are used to switch the pin functions. The operating mode is determined by the setting of the mode pins (MD2 to MD0). Modes 6 to 4 are external extended modes used to access external memory or peripheral devices.
Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to monitor the current operating mode of this LSI. Bit Bit Name Initial Value R/W Description 7 — 1 Reserved — This bit is always read as 1 and cannot be modified. 6 to 3 — All 0 — Reserved These bits are always read as 0 and cannot be modified.
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR is used to select the interrupt control mode and the detected edge for NMI, select the MRES input pin enable or disable, and enables or disables on-chip RAM. Bit Bit Name Initial Value R/W Description 7 — 0 R/W Reserved 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W The write value should always be 0. Reserved This bit is always read as 0 and cannot be modified.
Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. Pins P13 to P11 function as input ports immediately after a reset. Pin 10 and ports A and B function as address (A20 to A8) outputs immediately after a reset.
Section 3 MCU Operating Modes 3.3.3 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, and ports A, B, and C function as input ports immediately after a reset. Address (A23 to A8) output can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR) regardless of the corresponding data direction register (DDR) values.
Section 3 MCU Operating Modes 3.3.5 Pin Functions The pin functions of ports 1, and A to F vary depending on the operating mode. Table 3.2 shows their functions in each operating mode. Table 3.
Section 3 MCU Operating Modes 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.9 show the memory map in each operating mode.
Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) Mode 6 (advanced extended mode with on-chip ROM enabled) H'000000 H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space On-chip ROM H'01FFFF H'020000 Reserved H'040000 External address space Reserved* H'FFB000 Reserved* H'FFB000 H'FFD000 On-chip RAM* H'FFD000 H'FFEFC0 External address space H'FFEFC0 H'FFF800 On-chip RAM* External address space H'FFF800 Inter
Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) Mode 6 (advanced extended mode with on-chip ROM enabled) H'000000 H'000000 H'000000 External address space Mode 7 (advanced single-chip mode) On-chip ROM On-chip ROM H'05FFFF H'060000 H'FF7000 External address space H'FF7000 H'FF7000 On-chip RAM* On-chip RAM* On-chip RAM H'FFEFBF H'FFEFC0 External address space H'FFF800 H'FFEFC0 H'FFF800 Internal I/O registers External address space H'FFF800 In
Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) Mode 6 (advanced extended mode with on-chip ROM enabled) H'000000 H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space On-chip ROM H'03FFFF H'040000 H'FFB000 External address space H'FFB000 On-chip RAM* H'FFB000 On-chip RAM On-chip RAM* H'FFEFBF H'FFEFC0 External address space H'FFF800 H'FFEFC0 Internal I/O registers H'FFFF40 External address space H'FFFF60 In
Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) Mode 6 (advanced extended mode with on-chip ROM enabled) H'000000 H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space On-chip ROM H'01FFFF H'020000 Reserved H'040000 External address space Reserved* H'FFB000 Reserved* H'FFB000 H'FFD000 On-chip RAM* H'FFD000 H'FFEFC0 External address space H'FFEFC0 H'FFF800 On-chip RAM* External address space H'FFF800 Inter
Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) Mode 6 (advanced extended mode with on-chip ROM enabled) H'000000 H'000000 External address space Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'01FFFF H'020000 External address space H'FFB000 H'FFB000 On-chip RAM* H'FFB000 On-chip RAM* On-chip RAM H'FFEFBF H'FFEFC0 H'FFF800 External address space H'FFEFC0 External address space H'FFF800 Internal I/O registers Internal I/O
Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 Mode 6 (advanced extended mode with on-chip ROM enabled) On-chip ROM H'020000 H'FFB000 H'FFE000 H'FFEFC0 H'FFF800 H'000000 H'000000 Exter nal address space Reserved* On-chip RAM* External address space Mode 7 (advanced single-chip mode) H'FFB000 H'FFE000 H'FFEFC0 On-chip ROM H'01FFFF External address space Reserved* On-chip RAM* External address space H'FFF800 Internal I/O registers Intern
Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) Mode 6 (advanced extended mode with on-chip ROM enabled) H'000000 H'000000 H'000000 External address space Mode 7 (advanced single-chip mode) On-chip ROM On-chip ROM H'017FFF H'018000 Reserved H'020000 H'FFB000 H'FFE000 H'FFEFC0 H'FFF800 Reserved* On-chip RAM* External address space H'FFB000 H'FFE000 H'FFEFC0 External address space Reserved* On-chip RAM* External address space H'FFF800 Internal I/
Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 Mode 6 (advanced extended mode with on-chip ROM enabled) H'000000 H'000000 External address space Mode 7 (advanced single-chip mode) On-chip ROM On-chip ROM H'00FFFF H'010000 Reserved H'020000 H'FFB000 H'FFE000 H'FFEFC0 H'FFF800 Reserved* On-chip RAM* External address space H'FFB000 H'FFE000 H'FFEFC0 External address space Reserved* On-chip RAM* External address space H'FFF800 Internal I/O
Section 3 MCU Operating Modes Rev. 6.00 Mar.
Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exception handling requests are accepted at all times in program execution state.
Section 4 Exception Handling Table 4.
Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES or MRES pin goes low, all processing halts and this LSI enters the reset. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The interrupt control mode is 0 immediately after reset. When the RES or MRES pin goes high from the low state, this LSI starts reset exception handling. The chip can also be reset by overflow of the watchdog timer.
Section 4 Exception Handling 4.3.2 Reset Exception Handling When the RES or MRES pin goes low, this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES or MRES pin low for at least 20 states. When the RES or MRES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows. 1.
Section 4 Exception Handling 4.3.3 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx,SP). 4.3.
Section 4 Exception Handling Table 4.4 Status of CCR and EXR after Trace Exception Handling CCR EXR Interrupt Control Mode I UI 0 Trace exception handling cannot be used. 2 1 — I2 to I0 — T 0 Legend: 1: 0: —: 4.5 Set to 1 Cleared to 0 Retains value prior to execution Interrupts Interrupts are controlled by the interrupt controller.
Section 4 Exception Handling Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1 — — — 2 1 — — 0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution 4.7 Stack Status after Exception Handling Figures 4.
Section 4 Exception Handling 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features This LSI controls interrupts with the interrupt controller. The interrupt controller has the following features: • Two interrupt control modes ⎯ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR ⎯ An interrupt priority register (IPR) is provided for setting interrupt priorities.
Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. CPU INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISR ISCR IER Interrupt request Vector number Priority determination I CCR Internal interrupt request SWDTEND to TEI3 I2 to I0 IPR Interrupt controller Legend: ISCR: IER: ISR: IPR: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Figure 5.
Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt. Rising or falling edge can be selected. IRQ7 Input IRQ6 Input Maskable external interrupts. Rising, falling, or both edges, or level sensing can be selected. IRQ5 Input IRQ4 Input IRQ3 Input IRQ2 Input IRQ1 Input IRQ0 Input 5.
Section 5 Interrupt Controller • Interrupt priority register J (IPRJ) • Interrupt priority register K (IPRK) • Interrupt priority register L (IPRL) • Interrupt priority register O (IPRO) 5.3.1 Interrupt Priority Registers A to L, and O (IPRA to IPRL, IPRO) The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupt sources other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2.
Section 5 Interrupt Controller 5.3.2 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQn (n = 7 to 0). Bit Bit Name Initial Value R/W Description 7 IRQ7E 0 R/W IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. 6 IRQ6E 0 R/W IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1. 5 IRQ5E 0 R/W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1.
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 15 IRQ7SCB 0 R/W 14 IRQ7SCA 0 R/W IRQ7 Sense Control B IRQ7 Sense Control A 00: Interrupt request generated at IRQ7 input level low 01: Interrupt request generated at falling edge of IRQ7 input 10: Interrupt request generated at rising edge of IRQ7 input 11: Interrupt request generated at both falling and rising edges of IRQ7 input 13 IRQ6SCB 0 R/W 12 IRQ6SCA 0 R/W IRQ6 Sense Control B IRQ6 Sense Control A 00: I
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 7 IRQ3SCB 0 R/W 6 IRQ3SCA 0 R/W IRQ3 Sense Control B IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input level low 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input 5 IRQ2SCB 0 R/W 4 IRQ2SCA 0 R/W IRQ2 Sense Control B IRQ2 Sense Control A 00: Inter
Section 5 Interrupt Controller 5.3.4 IRQ Status Register (ISR) ISR indicates the status of IRQn (n = 7 to 0) interrupt requests. Bit 7 Bit Name IRQ7F Initial Value R/W Description 0 R/W* IRQ7 to IRQ0 Flags Indicates the status of IRQ7 to IRQ0 interrupt requests.
Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
Section 5 Interrupt Controller φ IRQn input pin IRQnF Note: n = 7 to 0 Figure 5.3 Set Timing for IRQnF The detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0; and use the pin as an I/O pin for another function. IRQnF interrupt request flag is set to 1 when the setting condition is satisfied, regardless of IER settings.
Section 5 Interrupt Controller Table 5.
Section 5 Interrupt Controller Vector Address*1 Origin of Interrupt Source Vector Number Advanced Mode IPR*2 Priority TGI0D (TGR0D input capture/compare-match) 35 H'008C IPRF6 to IPRF4 High TCI0V (overflow 0) 36 H'0090 ⎯ Reserved 37 38 39 H'0094 H'0098 H'009C TPU channel 1 TGI1A (TGR1A input capture/compare-match) 40 H'00A0 TGI1B (TGR1B input capture/compare-match) 41 H'00A4 TCI1V (overflow 1) 42 H'00A8 TCI1U (underflow 1) 43 H'00AC TGI2A (TGR2A input capture/compare-match) 44
Section 5 Interrupt Controller Vector Address*1 Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR*2 Priority ⎯ Reserved 53 H'00D4 IPRG2 to IPRG0 High 54 H'00D8 55 H'00DC TGI4A (TGR4A input capture/compare-match) 56 H'00E0 TGI4B (TGR4B input capture/compare-match) 57 H'00E4 TCI4V (overflow 4) 58 H'00E8 TCI4U (underflow 4) 59 H'00EC TGI5A (TGR5A input capture/compare-match) 60 H'00F0 TGI5B (TGR5B input capture/compare-match) 61 H'00F4 TCI5V (overflow
Section 5 Interrupt Controller Vector Address*1 Origin of Interrupt Source Interrupt Source DMAC*5 SCI channel 0 SCI channel 1 SCI channel 2*3 8-bit timer channel 2* ⎯ 4 Advanced Mode IPR*2 Priority DEND0A (completion of 72 channel 0/channel 0A transfer) H'0120 IPRJ6 to IPRJ4 High DEND0B (completion of channel 0B transfer) 73 H'0124 DEND1A (completion of 74 channel 1/channel 1A transfer) H'0128 DEND1B (completion of channel 1B transfer) 75 H'012C ERI0 (receive error 0) 80 H'0140 RX
Section 5 Interrupt Controller Vector Address*1 Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR*2 Priority IPRL6 to IPRL4 High 8-bit timer channel 3*4 CMIA3 (compare-match A3) 96 H'0180 CMIB3 (compare-match B3) 97 H'0184 OVI3 (overflow 3) 98 H'0188 ⎯ Reserved 99 H'018C IIC channel 0*4 (option) IICI0 (1-byte transmission/ reception completion) 100 H'0190 Reserved 101 H'0194 IICI1 (1-byte transmission/ reception completion) 102 H'0198 Reserved 103 H
Section 5 Interrupt Controller 5.5 Operation 5.5.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in this LSI differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip peripheral module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request.
Section 5 Interrupt Controller Figure 5.4 shows the block diagram of the priority decision circuits. Interrupt control mode 0 I Interrupt acceptance control Default priority determination Interrupt source Vector number 8-level mask control IPR I2 to I0 Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.
Section 5 Interrupt Controller The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.5 Interrupts Selected in Each Interrupt Control Mode (2) Interrupt Control Mode Selected Interrupts 0 All interrupts 2 Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0).
Section 5 Interrupt Controller 5.5.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts, IRQ interrupts and on-chip peripheral module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. 1.
Section 5 Interrupt Controller Program execution status Interrupt generated No Yes Yes NMI No No Hold pending I=0 Yes IRQ0 No No Yes IRQ1 Yes TEI3 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 6.00 Mar.
Section 5 Interrupt Controller 5.5.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts, and on-chip peripheral module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2.
Section 5 Interrupt Controller Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Level 6 interrupt? No No Yes Level 1 interrupt? Yes Mask level 5 or below? No No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 5.5.
(1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed.
Section 5 Interrupt Controller 5.5.5 Interrupt Response Times This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.7 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.7 are explained in table 5.8. Table 5.
Section 5 Interrupt Controller Table 5.8 Number of States in Interrupt Handling Routine Execution Status Object of Access External Device 8 Bit Bus Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK 16 Bit Bus Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access 1 4 6+2m 2 3+m Legend: m: Number of wait states in an external device access. 5.5.6 DTC and DMAC* Activation by Interrupt The DTC and DMAC* can be started by interrupts.
Section 5 Interrupt Controller Stop signal Clear signal DMAC* DTC start request vector number Interrupt request Selection circuit IRQ interrupt Interrupt source Internal clear signal peripheral function modules Selection signal Clear signal DTCER Control logic DTC Clear signal DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, I2 to I0 Interrupt controller Note: * Supported only by the H8S/2239 Group. Figure 5.
Section 5 Interrupt Controller (2) Determination of priority The DTC startup source is selected according to the default priority. This is not influenced by the mask level or the priority level. See section 9.4, Location of Register Information and DTC Vector Table, for details on these priorities. The startup sources are directly input to each channel in the DMAC*. Note: * Supported only by the H8S/2239 Group.
Section 5 Interrupt Controller (4) Usage Notes The SCI and A/D converter interrupt sources are cleared when the DMAC* or DTC reads or writes the stipulated register. This does not depend on the DTA, DTCE, and DISEL bits. Note: * Supported only by the H8S/2239 Group. 5.6 Usage Notes 5.6.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction.
Section 5 Interrupt Controller TCR write cycle by CPU CMIA exception handling φ Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.9 Contention between Interrupt Generation and Disabling 5.6.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed.
Section 5 Interrupt Controller With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W 5.6.5 MOV.
Section 6 PC Break Controller (PBC) Section 6 PC Break Controller (PBC) The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. A block diagram of the PC break controller is shown in figure 6.1. 6.
Section 6 PC Break Controller (PBC) BCRA Output control BARA Mask control Control logic Comparator Match signal Internal address PC break interrupt Access status Control logic Comparator Output control Match signal Mask control BARB BCRB Figure 6.1 Block Diagram of PC Break Controller 6.2 Register Descriptions The PC break controller has the following registers.
Section 6 PC Break Controller (PBC) 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) BCRA controls channel A PC breaks.
Section 6 PC Break Controller (PBC) Bit Bit Name Initial Value R/W 0 BIEA 0 R/W Description Break Interrupt Enable When this bit is 1, the PC break interrupt request of channel A is enabled. Notes: 1. Only a 0 can be written to this bit to clear the flag. 2. Read the state wherein CMFA = 1 twice or more, when the CMFA is polled after inhibiting the PC break interruption. 3. Supported only by the H8S/2239 Group. 6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register.
Section 6 PC Break Controller (PBC) 6.3.2 PC Break Interrupt Due to Data Access 1. Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack operations and branch address reads are included in data accesses. 2. Set the break conditions in BCRA. Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 5 to 3 (BAMRA2 to 0).
Section 6 PC Break Controller (PBC) • When the SLEEP instruction causes a transition to software standby mode or watch mode: After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2 (D).
Section 6 PC Break Controller (PBC) Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the instruction will be one state later than in normal operation. 6.4 Usage Notes 6.4.1 Module Stop Mode Setting PBC operation can be disabled or enabled using the module stop control register. The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 6.4.
Section 6 PC Break Controller (PBC) 6.4.6 I Bit Set by LDC, ANDC, ORC, and XORC Instruction When the I bit is set by an LDC, ANDC, ORC, and XORC instruction, a PC break interrupt becomes valid two states after the end of the executing instruction. If a PC break interrupt is set for the instruction following one of these instructions, since interrupts, including NMI, are disabled for a 3-state period in the case of LDC, ANDC, ORC, and XOR, the next instruction is always executed.
Section 7 Bus Controller Section 7 Bus Controller This LSI has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC)*, and data transfer controller (DTC). Note: * Supported only by the H8S/2239 Group. 7.
Section 7 Bus Controller Figure 7.1 shows a block diagram of the bus controller.
Section 7 Bus Controller 7.2 Input/Output Pins Table 7.1 summarizes the pins of the bus controller. Table 7.1 Pin Configuration Name Symbol I/O Address strove AS Output Strobe signal indicating that address output on address bus is enabled. Read RD Output Strobe signal indicating that external space is being read. High write HWR Output Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled.
Section 7 Bus Controller 7.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR.
Section 7 Bus Controller 7.3.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. • WCRH Bit Bit Name Initial Value R/W Description 7 W71 1 R/W Area 7 Wait Control 1 and 0 6 W70 1 R/W These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1.
Section 7 Bus Controller Bit Bit Name Initial Value R/W Description 3 W51 1 R/W Area 5 Wait Control 1 and 0 2 W50 1 R/W These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1.
Section 7 Bus Controller Bit Bit Name Initial Value R/W Description 5 W21 1 R/W Area 2 Wait Control 1 and 0 4 W20 1 R/W These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1.
Section 7 Bus Controller 7.3.4 Bus Control Register H (BCRH) BCRH selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. Bit Bit Name Initial Value R/W Description 7 ICIS1 1 Idle Cycle Insert 1 R/W Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas.
Section 7 Bus Controller 7.3.5 Bus Control Register L (BCRL) BCRL performs selection of the external bus-released state protocol, and enabling or disabling of WAIT pin input. Bit Bit Name Initial Value R/W Description 7 BRLE 0 Bus release enable R/W Enables or disables external bus release. 0: External bus release is disabled. BREQ and BACK can be used as I/O ports 1: External bus release is enabled 6 — 0 R/W Reserved The write value should always be 0.
Section 7 Bus Controller 7.3.6 Bit Pin Function Control Register (PFCR) Bit Name 7, 6 ⎯ Initial Value R/W All 0 R/W Description Reserved The write value should always be 0. 5 BUZZE 0 R/W BUZZ Output Enable: This bit selects enabling or disabling of BUZZ output from pin PF1. WDT_1 input clock that is selected by PSS, and CKS2 to CKS0 bits is output as BUZZ signal. 0: PF1 input/output pin 1: BUZZ output pin 4 ⎯ 0 R/W Reserved The write value should always be 0.
Section 7 Bus Controller 7.4 Bus Control 7.4.1 Area Divisions In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 7 to 0, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 7.2 shows an outline of the memory map. Chip select signals (CS7 to CS0) can be output for each area. Note: * Not availoable in this LSI.
Section 7 Bus Controller 7.4.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR.
Section 7 Bus Controller Table 7.2 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL ABWn ASTn Wn1 Wn0 Bus Width Number of Access Number of Program States Wait States 0 0 ⎯ ⎯ 16 1 0 0 1 1 1 0 2 1 3 1 0 ⎯ ⎯ 1 0 0 1 7.4.3 Bus Specifications (Basic Bus Interface) 8 2 0 3 0 2 0 3 0 1 1 0 2 1 3 Bus Interface for Each Area The initial state of each area is basic bus interface, 3-state access space.
Section 7 Bus Controller Only the basic bus interface can be used for the area 7. 7.4.4 Chip Select Signals This LSI can output chip select signals (CS7 to CS0) to areas 7 to 0, the signal being driven low when the corresponding external space area is accessed. Figure 7.3 shows an example of CSn (n = 7 to 0) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin.
Section 7 Bus Controller 7.5.1 On-Chip Memory (ROM, RAM) Access Timing On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 7.4 shows the on-chip memory access cycle. Figure 7.5 shows the pin states. Bus cycle T1 φ Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 7.
Section 7 Bus Controller 7.5.2 On-Chip Peripheral Module Access Timing The on-chip peripheral modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 7.6 shows the access timing for the on-chip peripheral modules. Figure 7.7 shows the pin states.
Section 7 Bus Controller 7.5.3 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 7.6.3, Basic Timing. 7.6 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 7.6.
Section 7 Bus Controller In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus Lower data bus D15 D8 D7 D0 Byte size • Even address Byte size • Odd address Word size 1st bus cycle Longword size 2nd bus cycle Figure 7.9 Access Sizes and Data Alignment Control (16-Bit Access Space) 7.6.2 Valid Strobes Table 7.
Section 7 Bus Controller 7.6.3 Basic Timing 8-Bit 2-State Access Space: Figure 7.10 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR (16-bit bus mode) Write LWR (8-bit bus mode) D15 to D8 D7 to D0 High High impedance Valid High impedance Note: n = 7 to 0 Figure 7.
Section 7 Bus Controller 8-Bit 3-State Access Space: Figure 7.11 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR (16-bit bus mode) Write LWR (8-bit bus mode) D15 to D8 D7 to D0 High High impedance Valid High impedance Note: n = 7 to 0 Figure 7.
Section 7 Bus Controller 16-Bit 2-State Access Space: Figures 7.12 to 7.14 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 7 to 0 Figure 7.
Section 7 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write High impedance D15 to D8 D7 to D0 Valid Note: n = 7 to 0 Figure 7.13 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev. 6.00 Mar.
Section 7 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 7 to 0 Figure 7.14 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev. 6.00 Mar.
Section 7 Bus Controller 16-Bit 3-State Access Space: Figures 7.15 to 7.17 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 7 to 0 Figure 7.
Section 7 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 7 to 0 Figure 7.16 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev. 6.00 Mar.
Section 7 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 7 to 0 Figure 7.17 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) 7.6.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin.
Section 7 Bus Controller (2) Pin Wait Insertion Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, program wait insertion is first carried out according to the settings in WCRH and WCRL. Then, if the WAIT pin is low at the falling edge of φ in the last T2 or TW state, a TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high. Figure 7.18 shows an example of wait state insertion timing.
Section 7 Bus Controller 7.7 Burst ROM Interface With this LSI, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only.
Section 7 Bus Controller Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Only lower address changed Address bus CS0 AS RD Data bus Read data Read data Read data Figure 7.19 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Full access T1 T2 Burst access T1 T1 φ Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 7.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) Rev. 6.00 Mar.
Section 7 Bus Controller 7.7.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.6.4, Wait Control. Wait states cannot be inserted in a burst cycle. 7.
Section 7 Bus Controller (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7.22 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data.
Section 7 Bus Controller Bus cycle A φ T1 T2 T3 Bus cycle B T1 Bus cycle A T2 φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD T1 T2 T3 Bus cycle B TI T1 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 7.23 Relationship between Chip Select (CS) and Read (RD) Table 7.4 shows pin states in an idle cycle. Table 7.
Section 7 Bus Controller 7.9 Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. In external extended mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to this LSI.
Section 7 Bus Controller Figure 7.24 shows the timing for transition to the bus-released state. CPU cycle T0 T1 CPU cycle External bus released state T2 φ High impedance Address bus Address High impedance Data bus High impedance CSn High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK Minimum 1 state [1] [1] [2] [3] [4] [5] [2] [3] [4] [5] Low level of BREQ pin is sampled at rise of T2 state.
Section 7 Bus Controller 7.10 Bus Arbitration This LSI has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DMAC*, and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
Section 7 Bus Controller 7.10.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus.
Section 7 Bus Controller 7.11 Resets and the Bus Controller In a power-on reset, this LSI, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset, the bus controller's registers and internal state are maintained, and an executing external bus cycle is completed. In this case, WAIT input is ignored and write data is not guaranteed. When the DMAC* is initialized at the manual reset, DACK and TEND output is disabled.
Section 7 Bus Controller Rev. 6.00 Mar.
Section 8 DMA Controller (DMAC) Section 8 DMA Controller (DMAC) The H8S/2239 Group has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. Note: The DMAC is supported only by the H8S/2239 Group. It is not available in the H8S/2258 Group, H8S/2238 Group, H8S/2237 Group, and H8S/2227 Group. 8.
Section 8 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 8.1.
Section 8 DMA Controller (DMAC) 8.2 Input/Output Pins Table 8.1 shows the pin configuration of the interrupt controller. Table 8.
Section 8 DMA Controller (DMAC) • DMA control register_1A (DMACR_1A) • DMA control register_1B (DMACR_1B) • DMA band control register H (DMABCRH) • DMA band control register L (DMABCRL) • DMA write enable register (DMAWER) • DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode). The transfer mode can be selected by means of the FAE1 and FAE0 bits in DMABCRH.
Section 8 DMA Controller (DMAC) 8.3.1 Memory Address Registers (MARA and MARB) MAR is a 32-bit readable/writable register that specifies the source address (transfer source address) or destination address (transfer destination address). MAR consists of two 16-bit registers MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified.
Section 8 DMA Controller (DMAC) IOAR can be used in short address mode but not in full address mode. 8.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0 (channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B). ETCR is not initialized by a reset or in standby mode.
Section 8 DMA Controller (DMAC) 8.3.4 DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B). In short address mode, channels A and B operate independently, and in full address mode, channels A and B operate together.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 RPE 0 R/W Repeat Enable Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and channel B.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Channel B: 2 DTF2 0 R/W 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by A/D converter conversion end interrupt 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmitdata-empty interrupt 0101: Activated by SCI channel 0 received
Section 8 DMA Controller (DMAC) (2) Full Address Mode • DMACR_0A and DMACR_1A Bit Bit Name Initial Value R/W Description 15 DTSZ 0 R/W Data Transfer Size Selects the size of data to be transferred at one time.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 12 BLKDIR 0 R/W Block Direction 11 BLKE 0 R/W Block Enable These bits specify whether normal mode or block transfer mode is to be used for data transfer. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area.
Section 8 DMA Controller (DMAC) • DMACR_0B and DMACR_1B Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 6 5 DAID DAIDE 0 0 R/W R/W Destination Address Increment/Decrement Destination Address Increment/Decrement Enable These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Block Transfer Mode 2 DTF2 0 R/W 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by A/D converter conversion end interrupt 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmitdata-empty interrupt 0101: Activated by SCI channel 0
Section 8 DMA Controller (DMAC) 8.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL) DMABCR controls the operation of each DMAC channel. The bit functions in the DMACR registers differ according to the transfer mode. (1) Short Address Mode • DMABCRH Bit Bit Name Initial Value R/W Description 15 FAE1 0 R/W Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 11 DTA1B 0 R/W Data Transfer Acknowledge 1B 10 DTA1A 0 R/W Data Transfer Acknowledge 1A 9 DTA0B 0 R/W Data Transfer Acknowledge 0B 8 DTA0A 0 R/W Data Transfer Acknowledge 0A These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR.
Section 8 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTE1B 0 R/W Data Transfer Enable 1B 6 DTE1A 0 R/W Data Transfer Enable 1A 5 DTE0B 0 R/W Data Transfer Enable 0B 4 DTE0A 0 R/W Data Transfer Enable 0A If the DTE bit is cleared to 0 when DTIE = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTIE1B 0 R/W 2 DTIE1A 0 R/W 1 DTIE0B 0 R/W Data Transfer End Interrupt Enable 1B Data Transfer End Interrupt Enable 1A Data Transfer End Interrupt Enable 0B Data Transfer End Interrupt Enable 0A 0 DTIE0A 0 R/W These bits enable or disable an interrupt to the CPU or DTC when transfer ends.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 13, 12 — All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 11 DTA1 0 R/W Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 9 DTA0 0 R/W Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE0 = 1 and DTA0 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC.
Section 8 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTME1 0 R/W Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel 1. If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 6 DTE1 0 R/W Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 DTME0 0 R/W Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel 0. If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 4 DTE0 0 R/W Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
Section 8 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE1 bit is cleared to 1 when DTIE1A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Section 8 DMA Controller (DMAC) 8.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned.
Section 8 DMA Controller (DMAC) chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of other channels. MAR_0AH First transfer area MAR_0AL IOAR_0A ETCR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B MAR_1AH MAR_1AL DTC IOAR_1A ETCR_1A MAR_1BH MAR_1BL IOAR_1B ETCR_1B DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B Second transfer area using chain transfer DMABCR Figure 8.
Section 8 DMA Controller (DMAC) 8.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The TEND pin is available only for channel B in short address mode. Except for the block transfer mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents reaches 0 regardless of the activation source.
Section 8 DMA Controller (DMAC) Table 8.
Section 8 DMA Controller (DMAC) priority channel is activated. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0 after completion of a transfer, an interrupt request from the selected activation source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant interrupt request is sent to the CPU or DTC.
Section 8 DMA Controller (DMAC) 8.5 Operation 8.5.1 Transfer Modes Table 8.4 lists the DMAC transfer modes. Table 8.4 DMAC Transfer Modes Transfer Mode Transfer Source Short address mode • Dual address mode • 1-byte or 1-word transfer for a single transfer request • Specify source and destination addresses to transfer data in two bus cycles.
Section 8 DMA Controller (DMAC) Transfer Mode Transfer Source Remarks Full address mode • Auto-request • • External request • TPU channel 0 to 5 compare match/input capture A interrupt • SCI transmit-dataempty interrupt Normal mode (1) Auto-request • Transfer request is internally held • Number of transfers (1 to 65,536) is continuously sent • Burst/cycle steal transfer can be selected (2) External request • 1-byte or 1-word transfer for a single transfer request • Number of transfers:
Section 8 DMA Controller (DMAC) 8.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 8.5 summarizes register functions in sequential mode. Table 8.
Section 8 DMA Controller (DMAC) Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + ( 1)DTID (2DTSZ (N Where : L = Value set in MAR N = Value set in ETCR 1)) Figure 8.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends.
Section 8 DMA Controller (DMAC) [1] Sequential mode setting Set each bit in DMABCRH. Clear the FAE bit to 0 to select short address mode. Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. Set transfer source and transfer destination addresses [2] [3] Set the number of transfers in ETCR. [4] Set each bit in DMACR. Set the transfer data size with the DTSZ bit.
Section 8 DMA Controller (DMAC) 8.5.3 Idle Mode Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 8.6 summarizes register functions in idle mode. Table 8.
Section 8 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmit-data-empty and receive-data-full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Figure 8.6 shows an example of the setting procedure for idle mode. [1] Idle mode setting Set each bit in DMABCRH. Clear the FAE bit to 0 to select short address mode.
Section 8 DMA Controller (DMAC) 8.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRL. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues.
Section 8 DMA Controller (DMAC) restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1) DTID ·2 DTSZ · ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is not sent to the CPU or DTC.
Section 8 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmit-data-empty and receive-data-full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Figure 8.8 shows an example of the setting procedure for repeat mode. [1] Repeat mode setting Set each bit in DMABCRH. Clear the FAE bit to 0 to select short address mode.
Section 8 DMA Controller (DMAC) 8.5.5 Single Address Mode DMAC supports the dual address mode, in which two different cycles are used for reading and writing, and the single address mode, in which a single cycle is used for both reading and writing. In dual address mode, the source address and the destination address are specified respectively for transferring data.
Section 8 DMA Controller (DMAC) Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCRH to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 8.8 summarizes register functions in single address mode. Table 8.
Section 8 DMA Controller (DMAC) Figure 8.10 illustrates operation in single address mode (when sequential mode is specified). Address T DACK Transfer 1 byte or word transfer performed in response to 1 transfer request Legend: Address Address Where : Address B T B L N =L = L + ( 1)DTID (2DTSZ (N = Value set in MAR = Value set in ETCR 1)) Figure 8.10 Operation in Single Address Mode (when Sequential Mode Is Specified) Figure 8.
Section 8 DMA Controller (DMAC) [1] Single address mode setting Set each bit in DMABCRH. Clear the FAE bit to 0 to select short address mode. Set the SAE bit to 1 to select single address mode. Set DMABCRH Specify enabling or disabling of internal [1] interrupt clearing with the DTA bit. [2] Set transfer source and transfer destination addresses Set the transfer source address/transfer destination address in MAR. [2] [3] Set the number of transfers in ETCR. [4] Set each bit in DMACR.
Section 8 DMA Controller (DMAC) 8.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 8.
Section 8 DMA Controller (DMAC) Figure 8.12 illustrates operation in normal mode. Transfer Address TA Address TB Address BB Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N = LA = LB = LA + SAIDE ( 1)SAID (2DTSZ (N = LB + DAIDE ( 1)DAID (2DTSZ (N = Value set in MARA = Value set in MARB = Value set in ETCRA 1)) 1)) Figure 8.12 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests.
Section 8 DMA Controller (DMAC) Figure 8.13 shows an example of the setting procedure for normal mode. [1] Normal mode setting Set each bit in DMABCRH. Set the FAE bit to 1 to select full address mode. Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. Set transfer source and transfer destination addresses [2] [3] Set the number of transfers in ETCRA.
Section 8 DMA Controller (DMAC) 8.5.7 Block Transfer Mode In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB.
Section 8 DMA Controller (DMAC) Address TB Address TA 1st block 2nd block Transfer Block area Consecutive transfer of M bytes or words is performed in response to one request Nth block Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE ( 1)SAID (2DTSZ (M N 1)) = LB + DAIDE ( 1)DAID (2DTSZ (N 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 8.
Section 8 DMA Controller (DMAC) Figure 8.15 illustrates operation in block transfer mode when MARA is designated as a block area.
Section 8 DMA Controller (DMAC) ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 8.16 shows the operation flow in block transfer mode.
Section 8 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmit-data-empty and receive-data-full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 8.17 shows an example of the setting procedure for block transfer mode. [1] Block transfer mode setting Set each bit in DMABCRH. Set the FAE bit to 1 to select full address mode.
Section 8 DMA Controller (DMAC) 8.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 8.18. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations.
Section 8 DMA Controller (DMAC) 8.5.9 DMA Transfer (Dual Address Mode) Bus Cycles Short Address Mode: Figure 8.19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.
Section 8 DMA Controller (DMAC) DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.20 Example of Full Address Mode Transfer (Cycle Steal) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one bus cycle is executed by the CPU or DTC.
Section 8 DMA Controller (DMAC) DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Last transfer cycle Bus release Bus release Burst transfer Figure 8.21 Example of Full Address Mode Transfer (Burst Mode) In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.
Section 8 DMA Controller (DMAC) DMA read DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Block transfer Bus release Last block transfer Bus release Figure 8.22 Example of Full Address Mode Transfer (Block Transfer Mode) A one-block transfer is performed for a single transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
Section 8 DMA Controller (DMAC) Figure 8.23 shows an example of normal mode transfer activated by the DREQ pin falling edge.
Section 8 DMA Controller (DMAC) Figure 8.24 shows an example of block transfer mode transfer activated by the DREQ pin falling edge.
Section 8 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing (Normal Mode): Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 8.25 shows an example of normal mode transfer activated by the DREQ pin low level.
Section 8 DMA Controller (DMAC) Figure 8.26 shows an example of block transfer mode transfer activated by DREQ pin low level.
Section 8 DMA Controller (DMAC) 8.5.10 DMA Transfer (Single Address Mode) Bus Cycles Single Address Mode (Read): Figure 8.27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA DMA read dead φ Address bus RD DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 8.
Section 8 DMA Controller (DMAC) Figure 8.28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA dead φ Address bus RD DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.
Section 8 DMA Controller (DMAC) Single Address Mode (Write): Figure 8.29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA DMA write dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 8.29 Example of Single Address Mode Transfer (Byte Write) Rev. 6.
Section 8 DMA Controller (DMAC) Figure 8.30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.
Section 8 DMA Controller (DMAC) Figure 8.31 shows an example of single address mode transfer activated by the DREQ pin falling edge.
Section 8 DMA Controller (DMAC) resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. DREQ Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 8.32 shows an example of single address mode transfer activated by the DREQ pin low level.
Section 8 DMA Controller (DMAC) DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared.
Section 8 DMA Controller (DMAC) DMA read DMA write DMA read DMA write DMA read DMA DMA write read φ Address bus RD HWR LWR DMA control Idle Read Channel 0A Idle Write Read Write Idle Read Write Read Request clear Channel 0B Request hold Selection Channel 1 Request hold Nonselection Bus release Channel 0A transfer Request clear Request hold Bus release Selection Channel 0B transfer Request clear Bus release Channel 1 transfer Figure 8.33 Example of Multi-Channel Transfer 8.5.
Section 8 DMA Controller (DMAC) If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 8.34 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer.
Section 8 DMA Controller (DMAC) [1] Forced termination of DMAC Clear the DTE bit in DMABCRL to 0. To prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Clear DTE bit to 0 [1] Forced termination Figure 8.35 Example of Procedure for Forcibly Terminating DMAC Operation 8.5.15 Clearing Full Address Mode Figure 8.36 shows the procedure for releasing and initializing a channel designated for full address mode.
Section 8 DMA Controller (DMAC) 8.6 Interrupt Sources The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 8.12 shows the interrupt sources and their priority order. Table 8.
Section 8 DMA Controller (DMAC) 8.7 Usage Notes 8.7.1 DMAC Register Access during Operation Except for forced termination of the DMAC, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
Section 8 DMA Controller (DMAC) • If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 8.39. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA read DMA write φ DMA internal address DMA control DMA register operation Idle [1] Transfe source Transfer destination Read Write Idle [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 8.
Section 8 DMA Controller (DMAC) In medium-speed mode, the DREQ pin is sampled at the rising edge of the medium clock. 8.7.4 Activation by Falling Edge on DREQ Pin DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
Section 8 DMA Controller (DMAC) 8.7.7 Channel Re-Setting To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively.
Section 8 DMA Controller (DMAC) Rev. 6.00 Mar.
Section 9 Data Transfer Controller (DTC) Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.
Section 9 Data Transfer Controller (DTC) Internal address bus On-chip RAM CPU interrupt request Register information MRA MRB CRA CRB DAR SAR DTC service request Control logic DTC DTVECR Interrupt request DTCERA to DTCERG and DTCERI Interrupt controller Internal data bus Legend: DTC mode registers A and B MRA, MRB: DTC transfer count registers A and B CRA, CRB: DTC source address register SAR: DTC destination address register DAR: DTCERA to DTCERG DTC enable registers A to G and I and DTCERI: DTC
Section 9 Data Transfer Controller (DTC) • DTC enable registers A to G, and I (DTCERA to DTCERG, and DTCERI) • DTC vector register (DTVECR) 9.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 SM1 Undefined ⎯ Source Address Mode 1 and 0 6 SM0 Undefined ⎯ These bits specify an SAR operation after a data transfer.
Section 9 Data Transfer Controller (DTC) Bit Bit Name Initial Value R/W Description 0 Sz Undefined ⎯ DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer Legend: ×: Don’t care 9.2.2 DTC Mode Register B (MRB) MRB is an 8-bit register that selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 CHNE Undefined ⎯ DTC Chain Transfer Enable This bit specifies a chain transfer. For details, refer to section 9.5.
Section 9 Data Transfer Controller (DTC) 9.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 9.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 9.2.
Section 9 Data Transfer Controller (DTC) 9.2.7 DTC Enable Registers A to G, and I (DTCERA to DTCERG, and DTCERI) DTCER is a set of registers to specify the DTC activation interrupt source, and comprised of eight registers; DTCERA to DTCERG, and DTCERI. The correspondence between interrupt sources and DTCE bits, and vector numbers generated by the interrupt controller are shown in table 9.2. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing.
Section 9 Data Transfer Controller (DTC) 9.2.8 DTC Vector Register (DTVECR) DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Bit Name Initial Value R/W 7 SWDTE 0 R/W Description DTC Software Activation Enable Enables or disables the DTC software activation. 0: Disables the DTC software activation. 1: Enables the DTC software activation.
Section 9 Data Transfer Controller (DTC) 9.3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0.
Section 9 Data Transfer Controller (DTC) Source flag cleared Clear controller Clear DTCER Clear request Select IRQ interrupt DTVECR Interrupt request DTC Selection circuit On-chip peripheral module CPU Interrupt controller Interrupt mask Figure 9.2 Block Diagram of DTC Activation Source Control 9.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).
Section 9 Data Transfer Controller (DTC) Lower address 0 Register information start address Chain transfer 1 2 MRA SAR MRB DAR 3 Register information CRB CRA MRA SAR MRB DAR Register information for 2nd transfer in chain transfer CRB CRA 4 bytes Figure 9.3 The Location of the DTC Register Information in the Address Space DTC vector address Register information start address Register information Chain transfer Figure 9.
Section 9 Data Transfer Controller (DTC) Table 9.
Section 9 Data Transfer Controller (DTC) Interrupt Source Origin of Interrupt Source DTC Vector Number Vector Address DTCE* 8-bit timer channel 1 CMIA1 68 H'0488 DTCED1 CMIB1 69 H'048A DTCED0 2 DMAC* DEND0A 72 H'0490 DTCEE7 DEND0A 73 H'0492 DTCEE6 DEND1A 74 H'0494 DTCEE5 DEND1A 75 H'0496 DTCEE4 SCI channel 0 RXI0 81 H'04A2 DTCEE3 TXI0 82 H'04A4 DTCEE2 SCI channel 1 RXI1 85 H'04AA DTCEE1 TXI1 86 H'04AC DTCEE0 SCI 4 channel 2* 1 RXI2 89 H'04B2 DTCEF7 TXI2
Section 9 Data Transfer Controller (DTC) 9.5 Operation Register information is stored in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to the memory. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, and block transfer mode.
Section 9 Data Transfer Controller (DTC) 9.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt can be requested. Table 9.3 lists the register information in normal mode. Figure 9.6 shows the memory mapping in normal mode. Table 9.
Section 9 Data Transfer Controller (DTC) Table 9.4 lists the register information in repeat mode. Figure 9.7 shows the memory mapping in repeat mode. Table 9.
Section 9 Data Transfer Controller (DTC) Table 9.5 lists the register information in block transfer mode. Figure 9.8 shows the memory mapping in block transfer mode. Table 9.
Section 9 Data Transfer Controller (DTC) 9.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.9 shows the memory map for chain transfer.
Section 9 Data Transfer Controller (DTC) 9.5.5 Interrupts An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
Section 9 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Vector read Read Write Read Write Address Transfer information read Transfer information write Figure 9.
Section 9 Data Transfer Controller (DTC) 9.5.7 Number of DTC Execution States Table 9.6 lists execution status for a single DTC data transfer, and table 9.7 shows the number of states required for each execution status. Table 9.6 DTC Execution Status Mode Vector Read I Register Information Read/Write Data Read J K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 Legend: N: Block size (initial setting of CRAH and CRAL) Table 9.
Section 9 Data Transfer Controller (DTC) For example, when the DTC vector address table is located in the on-chip ROM, normal mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. 9.6 Procedures for Using DTC 9.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1.
Section 9 Data Transfer Controller (DTC) 9.7 Examples of Use of the DTC 9.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
Section 9 Data Transfer Controller (DTC) 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6.
Section 9 Data Transfer Controller (DTC) Rev. 6.00 Mar.
Section 10 I/O Ports Section 10 I/O Ports Table 10.1 summarizes the port functions. The pins of each port also have other functions such as input/output or interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have DR and DDR registers.
Section 10 I/O Ports Table 10.
Section 10 I/O Ports Port Port 9 Description Mode 4 Mode5 Mode 6 Mode 7 Input/Output and Output Type General I/O port P97/DA1*2 also functioning as P96/ DA0*2 D/A converter*2 analog output pins Port A Port B Port C Port D General I/O port also functioning as SCI_2*2 I/O pins and address output pins PA3/A19/SCK2*2 PA3/SCK2*2 PA2/A18/RxD2*2 PA2/RxD2*2 PA1/A17/TxD2*2 PA1/TxD2*2 PA0/A16 PA0 General I/O port also functioning as TPU_5*2, TPU_4*2, TPU_3*2 I/O pins, and address output pins PB7
Section 10 I/O Ports Port Port E Port F Port G Description Mode 4 Mode5 Mode 6 Mode 7 General I/O port PE7/D7 also functioning as PE6/D6 data I/O pins PE5/D5 PE7 PE4/D4 PE4 PE3/D3 PE3 PE2/D2 PE2 PE1/D1 PE1 PE0/D0 PE0 PF7/φ PF7/φ AS PF6 General I/O port also functioning as interrupt input pins, bus control I/O pins, an A/D converter input pins and WDT output pins PF5 HWR PF4 PF3/LWR/ADTRG/IRQ3 PF3/ADTRG/IRQ3 PF2/WAIT PF2 PF1/BACK/BUZZ PF1/BUZZ PF0/BREQ/IRQ2 PF0/IRQ2 PG4 PG3
Section 10 I/O Ports 10.1 Port 1 Port 1 is an 8-bit I/O port and has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 register (PORT1) 10.1.1 Port 1 Data Direction Register (P1DDR) P1DDR specifies input or output of the port 1 pins using the individual bits. P1DDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.9.
Section 10 I/O Ports 10.1.2 Port 1 Data Register (P1DR) P1DR stores output data for port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. This register cannot be modified.
Section 10 I/O Ports 10.1.4 Pin Functions Port 1 pins also function as TPU I/O pins (TPU_0, TPU_1, and TPU_2), DMAC* output pins, interrupt input pins and address output pins. Values of the register and pin functions are shown below. Note: * Supported only by the H8S/2239 Group. • P17/TIOCB2/TCLKD The pin functions are switched as shown below according to the combination of the TPU channel 2 setting, TPSC2 to TPS0 bits in TCR_0 and TCR_5, and the P17DDR bit.
Section 10 I/O Ports • P15/TIOCB1/TCLKC The pin functions are switched as shown below according to the combination of the TPU channel 1 setting, TPSC2 to TPS0 bits in TCR_0, TCR_2, TCR_4, and TCR_5 and the P15DDR bit. TPU Channel 1 Setting* 1 Output ⎯ 0 TIOCB1 output pin P15 input pin P15DDR Pin functions Input or Initial Value 1 P15 output pin 2 TIOCB1 input pin* TCLKC input pin* 3 Notes: 1. For the setting of the TPU channel, see section 11, 16-Bit Timer Pulse Unit (TPU). 2.
Section 10 I/O Ports • P13/TIOCD0/TCLKB/A23 The pin functions are switched as shown below according to the combination of operating mode, the TPU channel 0 setting, TPSC2 to TPSC0 bits in TCR_0 to TCR_2, AE3 to AE0 bits in PFCR and the P13DDR bit.
Section 10 I/O Ports • P11/TIOCB0/DACK1/A21 The pin functions are switched as shown below according to the combination of operating 3 mode, the TPU channel 0 setting, AE3 to AE0 bits in PFCR, the SAE1 bit* in DMABCRH, and the P11DDR bit.
Section 10 I/O Ports 10.2 Port 3 Port 3 is a general 7-bit I/O port and has the following registers. The P34, P35, and SCK1 function as NMOS push/pull outputs.* • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 register (PORT3) • Port 3 open drain control register (P3ODR) Note: * Function as CMOS outputs in the H8S/2237 Group and H8S/2227 Group. 10.2.1 Port 3 Data Direction Register (P3DDR) P3DDR specifies input or output of the port 3 pins using the individual bits.
Section 10 I/O Ports 10.2.2 Port 3 Data Register (P3DR) P3DR stores output data for port 3 pins. Bit Bit Name Initial Value R/W Description 7 — Undefined — Reserved These bits are always read as undefined value. 6 P36DR 0 R/W 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 10.2.3 Output data for a pin is stored when the pin is specified as a general purpose output port.
Section 10 I/O Ports 10.2.4 Port 3 Open Drain Control Register (P3ODR) P3ODR controls on/off state of the PMOS for port 3 pins. Bit Bit Name Initial Value R/W Description 7 — Undefined — Reserved These bits are always read as undefined value. 6 P36ODR 0 R/W 5 P35ODR 0 R/W 4 P34ODR 0 R/W 3 P33ODR 0 R/W 2 P32ODR 0 R/W 1 P31ODR 0 R/W 0 P30ODR 0 R/W Note: 10.2.
Section 10 I/O Ports NMOS Off PMOS Off 0 1 Output Output Input Input (a) Open drain output type for P34, P35, SCK1, SCL0, and SDA0 pins (b) Open drain output type for P33 to P30, SCL1, and SDA1 pins Figure 10.1 Types of Open Drain Outputs The P34, P35, and SCK1 NMOS push-pull outputs will not output the Vcc level, regardless of the load, even if set to the high output state. External pull-up resistors are required to output the Vcc level. Notes: 1.
Section 10 I/O Ports • P35/SCK1/SCL0/IRQ5 3 The pin functions are switched as shown below according to the combination of the ICE bit* in ICCR_0 of IIC_0, the C/A bit in SMR_1 of SCI_1, CKE0 and CKE1 bits in SCR_1, and the P35DDR bit. To use this port as SCL0 I/O pin, clear the C/A bit, CKE1 bit, and CKE0 bit to 0. The SCL0 functions as NMOS open drain output and the pin can drive bus directly. When this pin is specified as the P35 output pin or SCK1 output pin, it functions as NMOS push/pull 4 output.
Section 10 I/O Ports • P33/TxD1/SCL1 2 The pin functions are switched as shown below according to the combination of the ICE bit* in ICCR_1 of IIC_1, the TE bit in SCR_1 of SCI_1, and the P33DDR bit. SCL1 functions as NMOS open drain output and can drive bus directly. ICE*2 0 TE 1 0 ⎯ 0 1 ⎯ ⎯ P33 input pin P33 output pin*1 TxD1 output pin*1 SCL1 I/O pin*2 P33DDR Pin functions 1 Notes: 1. When P33ODR is set to 1, it functions as NMOS open drain output. 2.
Section 10 I/O Ports • P30/TxD0 The pin functions are switched as shown below according to the combination of the TE bit in SCR_0 of SCI_0 and the P30DDR bit. TE 0 0 1 ⎯ P30 input pin P30 output pin* TxD0 output* P30DDR Pin functions Note: * 10.3 1 When P30ODR is set to 1, it functions as NMOS open drain output. Port 4 Port 4 is an 8-bit input port and has the following register. • Port 4 register (PORT4) 10.3.1 Port 4 Register (PORT4) PORT4 shows port 4 pin states.
Section 10 I/O Ports 10.4 Port 7 Port 7 is an 8-bit I/O port and has the following registers. • Port 7 data direction register (P7DDR) • Port 7 data register (P7DR) • Port 7 register (PORT7) 10.4.1 Port 7 Data Direction Register (P7DDR) P7DDR specifies input or output of the port 7 pins using the individual bits. P7DDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.9.
Section 10 I/O Ports 10.4.2 Port 7 Data Register (P7DR) P7DR stores output data for port 7 pins. Bit Bit Name Initial Value R/W Description 7 P77DR 0 R/W 6 P76DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 P75DR 0 R/W 4 P74DR 0 R/W 3 P73DR 0 R/W 2 P72DR 0 R/W 1 P71DR 0 R/W 0 P70DR 0 R/W 10.4.3 Port 7 Register (PORT7) PORT7 shows the pin states. This register cannot be modified.
Section 10 I/O Ports 10.4.4 Pin Functions 1 1 Port 7 pins also function as TMR I/O pins (TMR_0, TMR_1, TMR_2* , and TMR_3* ), bus 2 control output pin, SCI I/O pins, and DMAC* I/O pins. Values of the register and pin functions are shown below. Notes: 1. Not available in the H8S/2237 Group and H8S/2227 Group. 2. Supported only by the H8S/2239 Group. • P77/TxD3 The pin functions are switched as shown below according to the combination of the TE bit in SCR_3 of SCI_3 and the P77DDR bit.
Section 10 I/O Ports • P74/TMO2/MRES The pin functions are switched as shown below according to the combination of OS3 to OS0 bits in TCSR_2 of TMR_2*, the MRESE bit in SYSCR, and the P74DDR bit. MRESE 0 OS3 to OS0* ⎯ 1 ⎯ 0 P74 output pin TMO2* output MRES input 0 Pin functions * Any bit is 1 All bits are 0 P74DDR Note: 1 P74 input pin Not available in the H8S/2237 Group and H8S/2227 Group.
Section 10 I/O Ports • P71/TMRI23/TMCI23/DREQ1/CS5 The pin functions are switched as shown below according to the combination of operating mode and the P71DDR bit. Operating mode Modes 4 to 6 P71DDR Pin functions Mode 7 0 1 P71 input pin 1 TMRI23* , 1 * TMCI23 , 2 * DREQ1 input pin CS5 output pin ⎯ 0 1 P71 input pin P71 output pin 1 1 2 TMRI23* , TMCI23* , DREQ1* input pin Notes: 1. Not available in the H8S/2237 Group and H8S/2227 Group. 2. Supported only by the H8S/2239 Group.
Section 10 I/O Ports 10.5 Port 9 Port 9 is a 2-bit input-only port and has the following register. • Port 9 register (PORT9) 10.5.1 Port 9 Register (PORT9) PORT9 shows port 9 pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description P97 ⎯* R 6 P96 ⎯* R The pin states are always read when these bits are read. 5 to 0 ⎯ ⎯ R 7 Reserved These bits are always read as undefined value. Note: 10.5.2 * Determined by the states of pins P97 and P96.
Section 10 I/O Ports 10.6 Port A Port A is a 4-bit I/O port and has the following register. • Port A data direction register (PADDR) • Port A data register (PADR) • Port A register (PORTA) • Port A pull-up MOS control register (PAPCR) • Port A open drain control register (PAODR) 10.6.1 Port A Data Direction Register (PADDR) PADDR specifies input or output the port A pins using the individual bits. PADDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.6.3 Port A Register (PORTA) PORTA shows the pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4 — Undefined — Reserved These bits are always read as undefined value. PA2 —* —* R PA1 —* R PA0 —* R 3 PA3 2 1 0 Note: 10.6.4 * R If this bit is read while PADDR is set to 1, the PADR value is read. If this bit is read while PADDR is cleared, the PA3 pin states are read. Determined by the states of PA3 to PA0 pins.
Section 10 I/O Ports 10.6.6 Pin Functions Port A pins also function as an address output pin and SCI_2* I/O pins. The relationship between the value of register and pin is shown as below. Note: * Not available in the H8S/2227 Group. • PA3/A19/SCK2 The pin functions are switched as shown below according to the combination of operating mode, 2 AE3 to AE0 bits in PFCR, the C/A in SMR_2 of SCI_2* , CKE1 and CKE0 bits in SCR_2, and the PA3DDR bit.
Section 10 I/O Ports • PA2/A18/RxD2 The pin functions are switched as shown below according to the combination of operating 2 mode, AE3 to AE0 bits in PFCR, the RE bit in SCR_2 of SCI_2* , and the PA2DDR bit. Operating mode AE3 to AE0 Modes 4 to 6 B'1011 or B'11xx 2 ⎯ PA2DDR ⎯ RE* Pin functions A18 output pin Mode 7 ⎯ Other than (B'1011 or B'11xx) 0 0 1 1 PA2 input pin PA2 output 1 pin* 0 1 ⎯ 0 1 ⎯ 2 RxD2* input pin PA2 input pin PA2 output 1 pin* RxD2* input pin 2 Notes: 1.
Section 10 I/O Ports • PA0/A16 The pin functions are switched as shown below according to the combination of operating mode, AE3 to AE0 bits in PFCR and the PA0DDR bit. Operating mode Modes 4 to 6 AE3 to AE0 Other than Mode 7 ⎯ B'0xxx or B'1000 (B'0xxx or B'1000) ⎯ 0 1 0 1 A16 output pin PA0 input pin PA0 output pin* PA0 input pin PA0 output pin* PA0DDR Pin functions Note: 10.6.7 * When PA0ODR in PAODR is set to 1, the corresponding pin functions as NMOS open drain output.
Section 10 I/O Ports • Port B pull-up MOS control register (PBPCR) 10.7.1 Port B Data Direction Register (PBDDR) PBDDR specifies input or output the port B pins using the individual bits. PBDDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.9.4, Access Methods for Registers with Write-Only Bits.
Section 10 I/O Ports 10.7.3 Port B Register (PORTB) PORTB shows the pin states and cannot be modified. Bit Bit Name Initial Value R/W Description 7 PB7 R 6 PB6 ⎯* ⎯* PB5 ⎯* R If these bits are read while the corresponding PBDDR bits are set to 1, the PBDR value is read. If these bits are read while PBDDR bits are cleared to 0, the pin states are read. PB4 ⎯* R 3 PB3 ⎯* R 2 PB2 R 1 PB1 ⎯* ⎯* 0 PB0 ⎯* R 5 4 Note: 10.7.
Section 10 I/O Ports • PB7/A15/TIOCB5 The pin functions are switched as shown below according to the combination of operating 3 mode, the TPU channel 5* setting, AE3 to AE0 bits in PFCR, and the PB7DDR bit.
Section 10 I/O Ports • PB5/A13/TIOCB4 The pin functions are switched as shown below according to the combination of operating 3 mode, the TPU channel 4* setting, AE3 to AE0 bits in PFCR, and the PB5DDR bit.
Section 10 I/O Ports • PB3/A11/TIOCD3 The pin function is switched as shown below according to combination of the operating mode, 3 the TPU channel 3* setting, AE3 to AE0 bits in PFCR, and the PB3DDR bit.
Section 10 I/O Ports • PB1/A9/TIOCB3 The pin functions are switched as shown below according to the combination of operating mode, 3 the TPU channel 3* setting, AE3 to AE0 bits in PFCR, and the PB1DDR bit.
Section 10 I/O Ports 10.7.6 Input Pull-Up MOS States in Port B Port B has a built-in input pull-up MOS function that can be controlled by software. Input pull-up MOS can be specified as on or off on an individual bit basis. Table 10.3 summarizes the input pull-up MOS states. Table 10.
Section 10 I/O Ports 10.8.1 Port C Data Direction Register (PCDDR) PCDDR specifies input or output the port C pins using the individual bits. PCDDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.9.4, Access Methods for Registers with Write-Only Bits.
Section 10 I/O Ports 10.8.3 Port C Register (PORTC) PORTC shows port C pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 PC7 ⎯* R 6 PC6 R 5 PC5 ⎯* ⎯* If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. 4 PC4 ⎯* R 3 PC3 R 2 PC2 ⎯* ⎯* PC1 ⎯* R PC0 ⎯* R 1 0 Note: 10.8.
Section 10 I/O Ports 10.8.5 Pin Functions Port C pins also function as address output pin. The values of register and pin functions are shown below. • PC7/A7, PC6/A6, PC5/A5, PC4/A4, PC3/A3, PC2/A2, PC1/A1, PC0/A0 The pin functions are switched as shown below according to the combination of operating mode and the PCnDDR bit.
Section 10 I/O Ports 10.9 Port D Port D is an 8-bit I/O port and has the following registers. • Port D data direction register (PDDDR) • Port D data register (PDDR) • Port D register (PORTD) • Port D pull-up MOS control register (PDPCR) 10.9.1 Port D Data Direction Register (PDDDR) PDDDR specifies input or output the port D pins using the individual bits. PDDDR cannot be read; if it is, an undefined value will be read.
Section 10 I/O Ports 10.9.2 Port D Data Register (PDDR) PDDR stores output data for port D pins. Bit Bit Name Initial Value R/W Description 7 PD7DR 0 R/W 6 PD6DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W 10.9.3 Port D Register (PORTD) PORTD shows port D pin states. This register cannot be modified.
Section 10 I/O Ports 10.9.4 Port D Pull-Up MOS Control Register (PDPCR) PDPCR controls the on/off state of port D input pull-up MOS. Bit Bit Name Initial Value R/W Description 7 PD7PCR 0 R/W 6 PD6PCR 0 R/W When a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PD5PCR 0 R/W 4 PD4PCR 0 R/W 3 PD3PCR 0 R/W 2 PD2PCR 0 R/W 1 PD1PCR 0 R/W 0 PD0PCR 0 R/W 10.9.
Section 10 I/O Ports 10.9.6 Input Pull-Up MOS States in Port D Port D has a built-in input pull-up MOS function that can be controlled by software. Input pull-up MOS can be used in mode 7 and specified as on or off on an individual bit basis. Table 10.5 summarizes the input pull-up MOS states in port D. Table 10.
Section 10 I/O Ports 10.10.1 Port E Data Direction Register (PEDDR) PEDDR specifies input or output of the port E pins using the individual bits. PEDDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.9.4, Access Methods for Registers with Write-Only Bits.
Section 10 I/O Ports 10.10.3 Port E Register (PORTE) PORTE shows port E pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 PE7 ⎯* R 6 PE6 R 5 PE5 ⎯* ⎯* If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read.
Section 10 I/O Ports 10.10.5 Pin Functions Port E pins also function as data I/O pins. The values of register and pin functions are shown below. • PE7/D7, PE6/D6, PE5/D5, PE4/D4, PE3/D3, PE2/D2, PE1/D1, PE0/D0 The pin functions are switched as shown below according to the combination of the operating mode, bus mode, and the PEnDDR bit.
Section 10 I/O Ports 10.11 Port F Port F is an 8-bit I/O port and has the following registers. • Port F data direction register (PFDDR) • Port F data register (PFDR) • Port F register (PORTF) 10.11.1 Port F Data Direction Register (PFDDR) PFDDR specifies input or output of the port F pins using the individual bits. PFDDR cannot be read; if it is, an undefined value will be read. This register is a write-only register, and cannot be written by bit manipulation instruction. For details, see section 2.9.
Section 10 I/O Ports 10.11.2 Port F Data Register (PFDR) PFDR stores output data for port F pins. PFDR stores output data for port F pins. Bit Bit Name Initial Value R/W Description 7 PF7DR 0 R/W 6 PF6DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose output port. 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W 10.11.3 Port F Register (PORTF) PORTF shows port F pin states.
Section 10 I/O Ports 10.11.4 Pin Functions Port F pins also function as bus control signal input/output pin, interrupt input pin, system clock output pin, A/D trigger input pin, and BUZZ output pin. The values of register and pin functions are shown below. • PF7/φ The pin functions are switched as shown below according to the PF7DDR bit.
Section 10 I/O Ports • PF3/LWR/ADTRG/IRQ3 The pin functions are switched as shown below according to the combination of operating mode and the PF3DDR bit. Operating mode Modes 4 to 6 Mode 7 ⎯ Bus mode 16-bit bus mode PF3DDR ⎯ 0 1 0 1 LWR output pin PF3 input pin PF3 output pin PF3 input pin PF3 output pin Pin functions 8-bit bus mode 1 ADTRG input pin* 2 IRQ3 input pin* Notes: 1. When TRGS0 and TRGS1 are set to 1, this pin is ADTRG input. 2.
Section 10 I/O Ports • PF0/BREQ/IRQ2 The pin functions are switched as shown below according to the combination of operating mode, the BRLE bit, and the PF0DDR bit. Operating mode Modes 4 to 6 BRLE Mode 7 0 0 1 ⎯ 0 1 PF0 input pin PF0 output pin BREQ input pin PF0 input pin PF0 output pin PF0DDR Pin functions ⎯ 1 IRQ2 input pin* Note: When this pin is used as an external interrupt pin, do not specify other functions. * 10.
Section 10 I/O Ports 10.12.2 Port G Data Register (PGDR) PGDR stores output data for port G pins. Bit Bit Name Initial Value R/W 7 to 5 ⎯ Undefined ⎯ 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 PG0DR 0 R/W Description Reserved These bits are always read as undefined value. Output data for a pin is stored when the pin is specified as a general purpose output port. 10.12.3 Port G Register (PORTG) PORTG shows port G pin states. This register cannot be modified.
Section 10 I/O Ports • PG4/CS0 The pin functions are switched as shown below according to the combination of operating mode and the PG4DDR bit. Operating mode Modes 4 to 6 PG4DDR Pin functions Mode 7 0 1 0 1 PG4 input pin CS0 output pin PG4 input pin PG4 output pin • PG3/Rx/CS1 The pin functions are switched as shown below according to the combination of the IEE bit in IECTR of IEB*, operating mode, and the PG3DDR bit.
Section 10 I/O Ports • PG1/CS3/IRQ7 The pin functions are switched as shown below according to the combination of operating mode and the PG1DDR bit. Operating mode Modes 4 to 6 PG1DDR Pin functions Note: * Mode 7 0 1 PG1 input pin CS3 output pin 0 1 PG1 input pin IRQ7 input pin* PG1 output pin When this pin is used as an external interrupt pin, do not specify other functions. • PG0/IRQ6 The pin functions are switched as shown below according to the PG0DDR bit.
Section 10 I/O Ports 10.13 Handling of Unused Pins Unused input pins should be fixed high or low. Generally, the input pins of CMOS products are high-impedance. Leaving unused pins open can cause the generation of intermediate levels due to peripheral noise induction. This can result in shoot-through current inside the device and cause it to malfunction. Table 10.7 lists examples of ways to handle unused pins. Pins marked NC should be left open. Table 10.
Section 11 16-Bit Timer Pulse Unit (TPU) Section 11 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels or six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 11.1 and figure 11.1, respectively. 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture 2 DMAC* TGRA_0 activation compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input ca
Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): TCNT TGRA TGRB TGRC TGRD TCNT TGRA TGRB Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U Internal data bus A/D conversion start request signal TCNT TGRA TGRB TCNT TGRA TGRB Bus interface TCNT TGRA TGRB TIER: TSR: TGR (A, B, C, D) : TCNT: TCNT TGRA TGRB TGRC TGRD Module data bus TSTR TSYR Channel 3 TCR TMDR TIORH TIORL TIER TSR Channel 4 TCR TMDR TIOR TIER TSR Ch
Internal data bus A/D conversion start request signal TCNT TGRA TGRB TCNT TGRA TGRB TGRC TGRD Module data bus TCNT TGRA TGRB Bus interface TSTR TSYR Common Channel 1 TCR TMDR TIOR TIER TSR Channel 0 TCR TMDR TIORH TIORL TIER TSR Channel 2 Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): Control logic for channels 0 to 2 Input/output pins Channel 0: TIOCA0 TIOCB0 TIOCC0 TIOCD0 Channel 1: TIOCA1 TIOCB1 Channel 2: TIOCA2 TIOCB2 TCR TMDR TIOR TIER TSR Clock input Internal clock: φ/1 φ/4 φ/16 φ/64 φ/256
Section 11 16-Bit Timer Pulse Unit (TPU) 11.2 Input/Output Pins Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3 Register Descriptions The TPU has the following registers in each channel.
Section 11 16-Bit Timer Pulse Unit (TPU) • Timer interrupt enable register_3 (TIER_3)* • Timer status register_3 (TSR_3)* • Timer counter_3 (TCNT_3)* • Timer general register A_3 (TGRA_3)* • Timer general register B_3 (TGRB_3)* • Timer general register C_3 (TGRC_3)* • Timer general register D_3 (TGRD_3)* • Timer control register_4 (TCR_4)* • Timer mode register_4 (TMDR_4)* • Timer I/O control register _4 (TIOR_4)* • Timer interrupt enable register_4 (TIER_4)* • Timer status register_4 (TSR_4)* • Timer coun
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU of the H8S/2227 Group has a total of three TCR registers, one each for channels 0 to 2. In other groups, the TPU has a total of six TCR registers, one each for channels 0 to 5. TCR register settings should be made only when TCNT operation is stopped.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.5 TPSC2 to TPSC0 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input 1 1 0 1 Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.2 Timer Mode Register (TMDR) The TMDR registers are used to set the operating mode for each channel. The TPU of the H8S/2227 Group has a total of three TMDR registers, one each for channels 0 to 2. In other groups, the TPU has a total of six TMDR registers, one each for channels 0 to 5. TMDR register settings should be made only when TCNT operation is stopped.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.11 MD3 to MD0 Bit 3 1 MD3* Bit 2 2 MD2* Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × — 1 1 0 1 1 × × Legend: ×: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3.
Section 11 16-Bit Timer Pulse Unit (TPU) TIORH_0, TIOR_1, TIOR_2, TIORH_3*, TIOR_4*, TIOR_5* Bit Bit Name Initial Value R/W Description 7 IOB3 0 R/W I/O Control B3 to B0 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W Specify the function of TGRB. For details, see tables 11.12, 11.14, 11.15, 11.16, 11.18, and 11.19. 3 IOA3 0 R/W I/O Control A3 to A0 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W Specify the function of TGRA. For details, see tables 11.20, 11.22, 11.23, 11.24, 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU of the H8S/2227 Group has a total of three TIER registers, one each for channels 0 to 2. In other groups, the TPU has a total of six TIER registers, one each for channels 0 to 5.
Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3*. In channels 1, 2, 4*, and 5*, bit 2 is reserved. It is always read as 0 and cannot be modified.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.5 Timer Status Register (TSR) The TSR registers indicate the status of each channel. The TPU of the H8S/2227 Group has a total of three TSR registers, one each for channels 0 to 2. In other groups, the TPU has a total of six TSR registers, one each for channels 0 to 5. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT 3 3 counts in channels 1, 2, 4* , and 5* .
Section 11 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit Name TGFD Initial value R/W 0 R/(W)* Description 1 Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3 3* . 3 3 In channels 1, 2, 4* , and 5* , bit 3 is reserved. It is always read as 0 and cannot be modified.
Section 11 16-Bit Timer Pulse Unit (TPU) Bit 1 Bit Name TGFB Initial value R/W 0 R/(W)* Description 1 Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU of the H8S/2227 Group has a total of three TCNT registers, one each for channels 0 to 2. In other groups, the TPU has a total of six TCNT registers, one each for channels 0 to 5. The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 11.3.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.9 Timer Synchronous Register (TSYR) In the H8S/2227 Group, TSYR selects independent or synchronous TCNT operation for channels 0 to 2. In other groups, TSYR selects independent or synchronous TCNT operation for channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description 7, 6 — All 0 R/W Reserved The write value should always be 0.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.4 Operation 11.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register.
Section 11 16-Bit Timer Pulse Unit (TPU) 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt.
Section 11 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software, DTC, or DMAC* activation TGF Note: * Supported only by the H8S/2239 Group. Figure 11.5 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. 1. Example of setting procedure for waveform output by compare match Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 2. Examples of waveform output operation Figure 11.7 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA TIOCB No change No change 0 output Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3*, and 4*, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Section 11 16-Bit Timer Pulse Unit (TPU) Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 11.10 Example of Input Capture Operation 11.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting).
Section 11 16-Bit Timer Pulse Unit (TPU) Synchronous operation selection Set synchronous operation [1] Synchronous presetting Set TCNT Synchronous clearing [2] Clearing source generation channel? No Yes Select counter clearing source [3] Set synchronous counter clearing [4] Start count [5] Start count [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation.
Section 11 16-Bit Timer Pulse Unit (TPU) For details on PWM modes, see section 11.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 Time H'0000 TIOCA0 TIOCA1 TIOCA2 Figure 11.12 Example of Synchronous Operation 11.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers.
Section 11 16-Bit Timer Pulse Unit (TPU) • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 11.13. Compare match signal Buffer register Timer general register Comparator TCNT Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Setting Procedure: Figure 11.15 shows an example of the buffer operation setting procedure. [1] Buffer operation Designate TGR as an input capture register or output compare register by means of TIOR. [2] Select TGR function [1] [3] Set buffer operation [2] Start count [3] Designate TGR for buffer operation with bits BFA and BFB in TMDR. Set the CST bit in TSTR to 1 to start the count operation. Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) TCNT value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 Time H'0000 TGRC_0 H'0200 H'0450 H'0520 Transfer TGRA_0 H'0200 H'0450 TIOCA Figure 11.16 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 11.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC.
Section 11 16-Bit Timer Pulse Unit (TPU) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA H'0532 TGRA TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 11.17 Example of Buffer Operation (2) 11.4.4 Cascaded Operation In cascaded operation*, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
Section 11 16-Bit Timer Pulse Unit (TPU) Example of Cascaded Operation Setting Procedure: Figure 11.18 shows an example of the setting procedure for cascaded operation. [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. Cascaded operation Set cascading [1] Start count [2] [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 FFFD TCNT_1 FFFE FFFF 0000 0000 0001 0002 0001 0000 0001 FFFF 0000 Figure 11.20 Example of Cascaded Operation (2) 11.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR.
Section 11 16-Bit Timer Pulse Unit (TPU) In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 11.30. Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 11.21 shows an example of the PWM mode setting procedure. [1] PWM mode Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in Select counter clock TCR. [1] [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
Section 11 16-Bit Timer Pulse Unit (TPU) TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 11.22 Example of PWM Mode Operation (1) Figure 11.23 shows an example of PWM mode 2 operation.
Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. In the H8S/2227 Group, this mode can be set for channels 1 and 2. In other groups, it can be set for channels 1, 2, 4, and 5.
Section 11 16-Bit Timer Pulse Unit (TPU) Example of Phase Counting Mode Setting Procedure: Figure 11.25 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. Phase counting mode Select phase counting mode [1] Start count [2] [2] Set the CST bit in TSTR to 1 to start the count operation. Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.32 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5*) TCLKC (Channels 2 and 4*) TCLKB (Channels 1 and 5*) TCLKD (Channels 2 and 4*) High level Operation Up-count Low level Low level High level Down-count High level Low level High level Low level Legend: : Rising edge : Falling edge Note: * Not available in the H8S/2227 Group. Rev. 6.00 Mar.
Section 11 16-Bit Timer Pulse Unit (TPU) 2. Phase counting mode 2 Figure 11.27 shows an example of phase counting mode 2 operation, and table 11.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5*) TCLKC (channels 2 and 4*) TCLKB (channels 1 and 5*) TCLKD (channels 2 and 4*) TCNT value Up-count Down-count Time Note: * Not available in the H8S/2227 Group. Figure 11.27 Example of Phase Counting Mode 2 Operation Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 3. Phase counting mode 3 Figure 11.28 shows an example of phase counting mode 3 operation, and table 11.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5*) TCLKC (channels 2 and 4*) TCLKB (channels 1 and 5*) TCLKD (channels 2 and 4*) TCNT value Down-count Up-count Time Note: * Not available in the H8S/2227 Group. Figure 11.28 Example of Phase Counting Mode 3 Operation Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 4. Phase counting mode 4 Figure 11.29 shows an example of phase counting mode 4 operation, and table 11.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5*) TCLKC (channels 2 and 4*) TCLKB (channels 1 and 5*) TCLKD (channels 2 and 4*) TCNT value Down-count Up-count Time Note: * Not available in the H8S/2227 Group. Figure 11.29 Example of Phase Counting Mode 4 Operation Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example: Figure 11.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.5 Interrupt Sources There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. In the H8S/2227 Group, the TPU has eight input capture/compare match interrupts, four for channel 0 and two each for channels 1 and 2.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.8 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started.
Section 11 16-Bit Timer Pulse Unit (TPU) φ External clock Falling edge Rising edge Falling edge TCNT input clock N−1 TCNT N N+1 N+2 Figure 11.32 Count Timing in External Clock Operation Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin.
Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture Signal Timing: Figure 11.34 shows input capture signal timing. φ Input capture input Input capture signal TCNT N N+1 N+2 N TGR N+2 Figure 11.34 Input Capture Input Signal Timing Timing for Counter Clearing by Compare Match/Input Capture: Figure 11.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 11.36 shows the timing when counter clearing by input capture occurrence is specified.
Section 11 16-Bit Timer Pulse Unit (TPU) φ Input capture signal Counter clear signal N TCNT H'0000 N TGR Figure 11.36 Counter Clear Timing (Input Capture) Buffer Operation Timing: Figures 11.37 and 11.38 show the timings in buffer operation. φ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 11.37 Buffer Operation Timing (Compare Match) Rev. 6.00 Mar.
Section 11 16-Bit Timer Pulse Unit (TPU) φ Input capture signal TCNT N TGRA, TGRB n N+1 TGRC, TGRD N N+1 n N Figure 11.38 Buffer Operation Timing (Input Capture) 11.9.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 11.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture: Figure 11.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. φ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 11.40 TGI Interrupt Timing (Input Capture) TCFV Flag/TCFU Flag Setting Timing: Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) φ TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 11.42 TCIU Interrupt Setting Timing Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC* is activated, the flag is cleared automatically. Figure 11.43 shows the timing for status flag clearing by the CPU, and figure 11.44 shows the timing for status flag clearing by the DTC or DMAC*.
Section 11 16-Bit Timer Pulse Unit (TPU) DTC/DMAC* read cycle T1 T2 DTC/DMAC* write cycle T1 T2 φ Address Source address Destination address Status flag Interrupt request signal Note: * Supported only by the H8S/2239 Group. Figure 11.44 Timing for Status Flag Clearing by DTC/DMAC* Activation Note: * Supported only by the H8S/2239 Group. 11.10 Usage Notes 11.10.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register.
Section 11 16-Bit Timer Pulse Unit (TPU) Overlap Phase Phase diffedifference Overlap rence Pulse width Pulse width TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Notes: Phase difference and overlap: 1.5 states or more Pulse width: 2.5 states or more Figure 11.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 11.10.
Section 11 16-Bit Timer Pulse Unit (TPU) TCNT write cycle T2 T1 φ TCNT address Address Write signal Counter clearing signal TCNT N H'0000 Figure 11.46 Contention between TCNT Write and Clear Operations 11.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.47 shows the timing in this case.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 11.48 shows the timing in this case. TGR write cycle T2 T1 φ TGR address Address Write signal Compare match signal Prohibited TCNT N N+1 TGR N M TGR write data Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) TGR write cycle T2 T1 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register N M N TGR Figure 11.49 Contention between Buffer Register Write and Compare Match 11.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11.50 shows the timing in this case.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.51 shows the timing in this case. TGR write cycle T2 T1 φ Address TGR address Write signal Input capture signal TCNT M M TGR Figure 11.51 Contention between TGR Write and Input Capture 11.10.
Section 11 16-Bit Timer Pulse Unit (TPU) Buffer register write cycle T2 T1 φ Buffer register address Address Write signal Input capture signal TCNT N M TGR Buffer register N M Figure 11.52 Contention between Buffer Register Write and Input Capture 11.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.54 shows the operation timing when there is contention between TCNT write and overflow.
Section 12 8-Bit Timers Section 12 8-Bit Timers The H8S/2258 Group, H8S/2239 Group, and H8S/2238 Group have an on-chip 8-bit timer module with four channels (TMR_0, TMR_1, TMR_2, and TMR_3) operating on the basis of an 8-bit counter. The H8S/2237 Group and H8S/2227 Group have an on-chip 8-bit timer module with two channels (TMR_0 and TMR_1) operating on the basis of an 8-bit counter.
Section 12 8-Bit Timers • Module stop mode can be set At initialization, the 8-bit timer operation is halted. Register access is enabled by canceling the module stop mode. Note: * Not available in the H8S/2237 Group and H8S/2227 Group. Figure 12.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
Section 12 8-Bit Timers 12.2 Input/Output Pins Table 12.1 summarizes the input and output pins of the 8-bit timer module. Table 12.
Section 12 8-Bit Timers • Time constant register A_3 (TCORA_3)* • Time constant register B_3 (TCORB_3)* • Timer control register_3 (TCR_3)* • Timer control/status register_3 (TCSR_3)* Note: * Not available in the H8S/2237 Group and H8S/2227 Group. 12.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit up-counter. TCNT_0 and TCNT_1 (TCNT_2 and TCNT_3)* comprise a single 16-bit register, so they can be accessed together by word access.
Section 12 8-Bit Timers 12.3.3 Time Constant Register B (TCORB) TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 (TCORB_2 and TCORB_3)* comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORB write cycle.
Section 12 8-Bit Timers Bit Bit Name Initial Value R/W Description 4 CCLR1 0 R/W Counter Clear 1 and 0 3 CCLR0 0 R/W These bits select the method by which TCNT is cleared. 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W The input clock can be selected from three clocks divided from the system clock (φ).
Section 12 8-Bit Timers 12.3.5 Timer Control/Status Register (TCSR) TCSR indicates status flags and controls compare-match output.
Section 12 8-Bit Timers Bit Bit Name Initial Value R/W Description 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT.
Section 12 8-Bit Timers • TCSR_1 and TCSR_3* 1 Bit Bit Name Initial Value R/W Description 7 CMFB 0 2 R/(W)* Compare-Match Flag B [Setting condition] When TCNT = TCORB [Clearing conditions] 6 CMFA 0 2 R/(W)* • Read CMFB when CMFB = 1, then write 0 in CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0 Compare-Match Flag A [Setting condition] When TCNT = TCORA [Clearing conditions] 5 OVF 0 2 R/(W)* • Read CMFA when
Section 12 8-Bit Timers Bit Bit Name Initial Value R/W Description 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT.
Section 12 8-Bit Timers • TCSR_2* 1 Bit Bit Name Initial Value R/W Description 7 CMFB 0 2 R/(W)* Compare-Match Flag B [Setting condition] When TCNT = TCORB [Clearing conditions] 6 CMFA 0 2 R/(W)* • Read CMFB when CMFB = 1, then write 0 in CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 with the transfer counter not being 0 Compare-Match Flag A [Setting condition] When TCNT = TCORA [Clearing conditions] 5 OVF 0 2 R/(W)* • Read CMFA when CMFA = 1, t
Section 12 8-Bit Timers Bit Bit Name Initial Value R/W Description 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT.
Section 12 8-Bit Timers TCNT H'FF Counter clear TCORA TCORB H'00 TMO Figure 12.2 Example of Pulse Output 12.5 Operation Timing 12.5.1 TCNT Incrementation Timing Figure 12.3 shows the TCNT count timing with internal clock source. Figure 12.4 shows the TCNT incrementation timing with external clock source. The pulse width of the external clock for incrementation at signal edge must be at least 1.5 system clock (φ) periods, and at least 2.5 states for incrementation at both edges.
Section 12 8-Bit Timers φ External clock input pin TCNT input clock N−1 TCNT N N+1 Figure 12.4 Count Timing for External Clock Input 12.5.2 Timing of CMFA and CMFB Setting when a Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match. The compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated.
Section 12 8-Bit Timers 12.5.3 Timing of Timer Output when a Compare-Match Occurs When a compare-match occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Figure 12.6 shows the timing when the output is set to toggle at comparematch A. φ Compare-match A signal Timer output pin Figure 12.6 Timing of Timer Output 12.5.
Section 12 8-Bit Timers 12.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 12.8 shows the timing of this operation. φ External reset input pin Clear signal N−1 TCNT N H'00 Figure 12.8 Timing of Clearing by External Reset Input 12.5.
Section 12 8-Bit Timers 12.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in one of TCR_0 and TCR_1 (TCR_2 and TCR_3)* are set to B'100, the 8bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer mode) or compare-matches of 8-bit channel 0 (channel 2)* can be counted by the timer of channel 1 (channel 3)* (compare-match count mode).
Section 12 8-Bit Timers 12.7 Interrupt Sources 12.7.1 Interrupt Sources and DTC Activation The 8-bit timer can generate three types of interrupt: CMIA, CMIB, and OVI. Table 12.2 shows the interrupt sources and priority. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR. Independent signals are sent to the interrupt controller for each interrupt. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 12.
Section 12 8-Bit Timers 12.8 Usage Notes 12.8.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.10 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 12.10 Contention between TCNT Write and Clear 12.8.
Section 12 8-Bit Timers TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.11 Contention between TCNT Write and Increment 12.8.3 Contention between TCOR Write and Compare-Match During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match occurs and the compare-match signal is disabled. Figure 12.12 shows this operation.
Section 12 8-Bit Timers 12.8.4 Contention between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 12.3. Table 12.3 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 12.8.
Section 12 8-Bit Timers Table 12.4 Switching of Internal Clock and TCNT Operation No. Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation 1 1 Switching from low to low* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 CKS bit rewrite 2 Switching from low to high* 2 Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Rev. 6.00 Mar.
Section 12 8-Bit Timers No. Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation 3 Switching from high to low* 3 Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. 12.8.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high.
Section 12 8-Bit Timers Rev. 6.00 Mar.
Section 13 Watchdog Timer (WDT) Section 13 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagram of the WDT is shown in figure 13.1. 13.
Section 13 Watchdog Timer (WDT) WOVI (interrupt request signal) Internal reset signal*1 Clock Clock select Reset control RSTCSR TCNT_0 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock sources*2 TCSR_0 Module bus Bus interface WDT Legend: TCSR_0: Timer control/status register0 TCNT_0: Timer counter0 RSTCSR: Reset control/status register Notes: 1. The type of internal reset signal depends on a register setting.
Section 13 Watchdog Timer (WDT) Interrupt control Internal NMI (interrupt request signal) Overflow Clock select Clock Reset control Internal reset signal* TCNT_1 BUZZ φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock sources TCSR_1 Bus interface Module bus φSUB/2 φSUB/4 φSUB/8 φSUB/16 φSUB/32 φSUB/64 φSUB/128 φSUB/256 Internal bus WOVI (interrupt request signal) WDT Legend: TCSR_1: Timer control/status register1 TCNT_1: Timer counter1 Note: * The type of internal reset signa
Section 13 Watchdog Timer (WDT) 13.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. To initialize TCNT to H'00 while the timer is operating, write H'00 to TCNT directly. See 13.6.7, Notes on Initializing TCNT by Using the TME Bit. 13.3.2 Timer Control/Status Register (TCSR) TCSR functions include selecting the clock source to be input to TCNT and the timer mode.
Section 13 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 0 to 2 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to TCNT. The 3 overflow frequency* for φ = 10 MHz is enclosed in parentheses. 000: Clock φ/2 (frequency: 51.2 μs) 001: Clock φ/64 (frequency: 1.6 ms) 010: Clock φ/128 (frequency: 3.2 ms) 011: Clock φ/512 (frequency: 13.2 ms) 100: Clock φ/2048 (frequency: 52.4 ms) 101: Clock φ/8192 (frequency: 209.
Section 13 Watchdog Timer (WDT) • TCSR_1 Bit Bit Name Initial Value 7 OVF 0 R/W Description R/(W) *1 Overflow Flag Indicates that TCNT has overflowed. Only a 0 can be written to this bit, to clear the flag. [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Section 13 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 0 to 2 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to TCNT. The 3 overflow frequency* for φ = 10 MHz is enclosed in parentheses. When PSS = 0: 000: Clock φ/2 (frequency: 51.2 μs) 001: Clock φ/64 (frequency: 1.6 ms) 010: Clock φ/128 (frequency: 3.2 ms) 011: Clock φ/512 (frequency: 13.2 ms) 100: Clock φ/2048 (frequency: 52.4 ms) 101: Clock φ/8192 (frequency: 209.
Section 13 Watchdog Timer (WDT) 13.3.3 Reset Control/Status Register (RSTCSR) (only WDT_0) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by overflows. Bit Bit Name 7 WOVF Initial Value R/W Description 0 R/(W)* Watchdog Overflow Flag This bit is set when TCNT overflows in watchdog timer mode.
Section 13 Watchdog Timer (WDT) 13.4 Operation 13.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. Thus, TCNT does not overflow while the system is operating normally.
Section 13 Watchdog Timer (WDT) TCNT value Overflow H'FF Time H'00 WT/IT=1 TME=1 Write H'00' to TCNT WOVF=1 WT/IT=1 TME=1 Write H'00' to TCNT internal reset is generated Internal reset signal* Legend: WT/IT: Timer mode select bit TME: Timer enable bit WOVF: Overflow flag 518 system clock (WDT0) 515/516 system clock (WDT1) Note: * In the case of WDT_0, the internal reset signal is generated only when the RSTE bit is set to 1.
Section 13 Watchdog Timer (WDT) TCNT value Overflow H'FF Overflow Overflow Overflow Time H'00 WT/IT=0 TME=1 WOVI WOVI WOVI WOVI Legend: WOVI: Interval timer interrupt request generation Figure 13.3 Interval Timer Mode Operation 13.4.3 Timing of Setting Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 13.4.
Section 13 Watchdog Timer (WDT) 13.4.4 Timing of Setting Watchdog Timer Overflow Flag (WOVF) With WDT_0 the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal is generated for the entire chip. (The WOVI interrupt is not generated.) This timing is illustrated in figure 13.5. φ TCNT H'FF H'00 Overflow signal (internal signal) WOVF Internal reset signal 518 states (WDT_0) 515/516 states (WDT_1) Figure 13.
Section 13 Watchdog Timer (WDT) 13.6 Usage Notes 13.6.1 Notes on Register Access The write method for TCNT, TCSR, and RSTCSR differs from that of normal registers so that they cannot be easily rewritten. Use the following procedures to read and write these registers. (1) Writing to TCNT and TCSR Word transfer instructions must be used to write to TCNT and TCSR. These registers cannot be written with byte transfer instructions. This is shown in figure 13.6.
Section 13 Watchdog Timer (WDT) When writing 0 to the WOVF bit Address: H'FF76 15 8 7 H'A5 0 H'00 When writing to the RSTE and RSTS bits 15 8 Address: H'FF76 H'5A 7 0 Write data Figure 13.7 Writing to RSTCSR (3) Reading from TCNT, TCSR, and RSTCSR These registers can be read in the same way normal registers are read. TCSR is allocated at address H'FF74, TCNT at address H'FF75, and RSTCSR at address H'FF77. 13.6.
Section 13 Watchdog Timer (WDT) 13.6.3 Changing Value of PSS or CKS2 to CKS0 If the PSS or CKS0 to CKS2 bits in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before changing the value of the PSS or CKS0 to CKS2 bits. 13.6.
Section 13 Watchdog Timer (WDT) Rev. 6.00 Mar.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] This LSI has an on-chip one-channel IEBus™ controller (IEB). The Inter Equipment Bus™ 1 (IEBus™)* is a small-scaled digital data transfer system for inter equipment data transfer. This LSI does not have an on-chip IEBus driver/receiver, so it is necessary to mount a dedicated 2 driver/receiver* externally. Notes: 1. IEBus is a trademark of NEC Electronics Corporation. 2.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Figure 14.1 shows an IEB block diagram.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.1.1 IEBus Communications Protocol The overview of the IEBus is described below. • Communications method: Half duplex asynchronous communications • Multi-master system All units connected to the IEBus can transfer data to other units.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (a) Priority according to communications type Broadcast communications (one-to-many communications) has priority over normal communications (one-to-one communications). (b) Priority according to master address A unit with the smallest master address has priority among units with the same communications type. Example: The master address is configured with 12 bits. A unit with H'000 has the highest priority, and a unit with H'FFF has the lowest priority.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (3) Communications Address In the IEBus, a 12-bit specific communications addresses are allocated to individual units. A communications address is configured as follows. • Upper four bits: group number (number identifying a group to which the unit belongs) • Lower eight bits: unit number (number identifying individual units in a group) (4) Broadcast Communications In normal transfer, a single master unit communicates with a single slave unit.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (When φ = 12 MHz) Field name Number of bits Header 1 1 Master Slave address address field field 12 1 12 1 1 Start Broad- Master bit cast address bit P Slave address P A Control field 4 Control bits 1 1 P A Message length field 8 1 1 Message length bits P A Data field 8 1 Data bits 1 P A 8 Data bits 1 1 P A Transfer time Mode 0 Approximately 7330 μs Approximately 1590 × N μs Mode 1 Approximately 2090 μs Approximately 410 × N μs
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] When more than one unit starts transfer of communications frame at the same timing, broadcast communications has priority over normal communications, and arbitration occurs. (2) Master Address Field The master address field is a field for transmitting the unit address (master address) to other units. The master address field is comprised of master address bits and a parity bit. The master address has 12 bits and are output MSB first.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] The slave unit returns the acknowledgement when the slave addresses match and the parities of the master and slave addresses are correct. When either of the parities of the master and slave addresses is wrong, the slave unit decides that the master or slave address is not correctly received and does not return the acknowledgement. In this case, the master unit enters the waiting (monitor) state, and communications end.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (5) Message Length Field The message length field is a field for specifying the number of transfer bytes. The message length field is comprised of message length bits, a parity bit, and an acknowledge bit. The message length has eight bits and is output MSB first. Table 14.3 shows the number of transfer bytes. Table 14.3 Contents of Message Length Bits Message Length bits (Hexadecimal) Number of Transfer Bytes H'01 1 byte H'02 . . 2 bytes . .
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (6) Data Field The data field is a field for data transmission/reception to the slave unit. The master unit transmits/receives data to/from the slave unit using the data field. The data field is comprised of data bits, a parity bit, and an acknowledge bit. The data bits include eight bits and are output MSB first. The parity bit and acknowledge bit following the data bits are output from the master unit and slave unit, respectively.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] acknowledgement. The master unit reads in the subsequent data if the number of data does not exceed the maximum number of transfer bytes in one frame. (7) Parity Bit The parity bit is used to confirm that transfer data has no error. The parity bit is added to respective data of the master address, slave address, control, message length, and data bits. The even parity is used. When the number of one bits in data is odd, the parity bit is 1.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] ⎯ When bit 3 in the control bits is 1 (data write) although the slave receive buffer* is not empty ⎯ When the control bits are set to the data read (H'3, H'7) although the slave transmit buffer* is empty ⎯ When another unit which locked the slave unit requests H'3, H'6, H'7, H'A, H'B, H'E, or H'F in the control bits although the slave unit has been locked ⎯ When the control bits are the locked address read (H'4, H'5) although the unit is not locked ⎯ When
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.1.3 Transfer Data (Data Field Contents) The data filed contents are specified by the control bits. Table 14.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Table 14.5 Control Field for Locked Slave Unit Setting Value Bit 3 Bit 2 Bit 1 Bit 0 Function H'0 0 0 0 0 Reads slave status H'4 0 1 0 0 Reads locked address (upper 8 bits) H'5 0 1 0 1 Reads locked address (lower 4 bits) (1) Slave Status Read (Control Bits: H'0, H'6) The master unit can decide the reason the slave unit does not return the acknowledgement (ACK) by reading the slave status (H'0, H'6).
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (2) Data Command Transfer (Control Bits: Read (H'3, H'7), Write (H'A, H'B, H'E, H'F)) In the case of data read (H'3, H'7), data in the data buffer of the slave unit is read in the master unit. In the case of data write (H'B or H'F) or command write (H'A or H'E), data received in the slave unit is processed in accordance with the operation specification of the slave unit. Notes: 1. The user can select data and commands freely in accordance with the system.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] in a single communications frame, the slave unit is unlocked by the master unit. In this case, a bit (bit 2) relevant to lock in the byte indicating the slave status is cleared to 0. Note that locking and unlocking are not performed in broadcast communications. Note: * There are three methods to unlock by a locked unit itself.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.2 Input/Output Pins Table 14.6 shows the IEB pin configuration. Table 14.6 Pin Configuration Name Abbreviation I/O Function IEBus transmit data pin Tx Output Transmit data output pin IEBus receive data pin Rx Input Receive data input pin 14.3 Register Descriptions The IEB has the following registers. For the module stop control register, see section 24.1.2, Module Stop Control Registers A to C (MSTPCRA to MSTPCRC).
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] • IEBus receive error flag register (IEREF) 14.3.1 IEBus Control Register (IECTR) IECTR controls IEB operation (switches IEBus pin/port functions, selects input/output level, and enables receive operation). Bit Bit Name Initial Value R/W Description 7 IEE 0 R/W IEB Pin Switch Switches IEB pin and port functions. 0: The PG3/Rx/CS1 and PG2/Tx/CS2 pins function as the PG3/CS1 and PG2/CS2 pins.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W 5 DEE 0 R/W Description Broadcast Receive Error Interrupt Enable Since the acknowledgement is not returned between the master and slave units in broadcast reception, the master unit cannot decide whether the slave unit is in the receive enabled state.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W 2 LUEE 0 R/W Description Last Byte Underrun Enable Sets whether to generate an underrun error when the last data field byte is transferred in data transmission. If the IEB reads from IETBR when the TxRDY flag is set (the transmit buffer register (IETBR) is empty), an underrun error occurs.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name 7 to 3 ⎯ Initial Value R/W All 0 ⎯ Description Reserved The read value is undefined. In order to avoid malfunction, do not use bit manipulation instructions. These bits cannot be modified. 2 CMD2 0 W Command Bits 1 CMD1 0 W 0 CMD0 0 W These bits issue a command to control IEB communications. When the CMX flag in IEFLG is set after the command issuance, the command is indicated to be in execution.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.3 IEBus Master Control Register (IEMCR) IEMCR sets communications conditions for master communications (selection of broadcast or normal communications, retransmission counts at arbitration loss, and control bits value). It is not necessary to set this register for slave communications.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W Description 3 1 CTL3* 0 R/W Control bits 2 CTL2 0 R/W 1 CTL1 0 R/W Set the control bits in the control field for master transmission. 0 CTL0 0 R/W 0000: Reads slave status 0001: Undefined. Setting prohibited. 0010: Undefined. Setting prohibited.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.4 IEBus Master Unit Address Register 1 (IEAR1) IEAR1 sets the lower 4 bits of the master unit address and communications mode. In master communications, the master unit address becomes the master address field value. In slave communications, the master unit address is compared with the received slave address field.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.5 IEBus Master Unit Address Register 2 (IEAR2) IEAR2 sets the upper 8 bits of the master unit address. In master communications, this register becomes the master address field value. In slave communications, this register is compared with the received slave address field. Bit Bit Name Initial Value R/W Description 7 IAR11 0 R/W Upper 8 Bits of IEBus Master Unit Address 6 IAR10 0 R/W Set the upper 8 bits of the master unit address.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.7 IEBus Slave Address Setting Register 2 (IESA2) IESA2 sets the upper 8 bits of the communications destination slave unit address. For slave communications, it is not necessary to set this register.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.9 IEBus Transmit Buffer Register (IETBR) IETBR is a 1-byte buffer to which data to be transmitted in master or slave transmission is written. IETBR is empty when the TxRDY flag in IETSR is 1. Check the TxRDY flag before setting transmit data in IETBR. Data written in IETBR is transmitted in the data field in master or slave transmission. Figure 14.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.10 IEBus Reception Master Address Register 1 (IEMA1) IEMA1 indicates the lower four bits of the communications destination master unit address in slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the contents are changed at the timing of setting the RxS flag in IERSR.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.12 IEBus Receive Control Field Register (IERCTL) IERCTL indicates the control field value in slave/broadcast reception. This register is enabled when slave/broadcast receive starts, and the contents are changed at the timing of setting the RxS flag in IERSR. This register cannot be modified. Bit Bit Name 7 to 4 ⎯ Initial Value R/W Description All 0 R Reserved These bits are always read as 0.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.14 IEBus Receive Buffer Register (IERBR) IERBR is a 1-byte read-only buffer that stores data received in master or slave reception. This register can be read when the RxRDY flag in IERSR is set to 1. This register indicates the data field value both in master and slave receptions. This register cannot be modified. Figure 14.7 shows the relationship between transmission signal format and registers in IEBus data reception.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.15 IEBus Lock Address Register 1 (IELA1) IELA1 specifies the lower 8 bits of a locked address when a unit is locked. Data in this register is valid when the LCK flag in IEFLG is set to 1. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7 ILA7 0 R Lower 8 Bits of IEBus Lock Address 6 ILA6 0 R 5 ILA5 0 R Store the lower 8 bits of the master unit address when a unit is locked.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.17 IEBus General Flag Register (IEFLG) IEFLG indicates the IEB command execution status, lock status and slave address match, and broadcast reception detection. This register cannot be modified. Bit Bit Name Initial Value R/W 7 CMX 0 R Description Command Execution Status Indicates the command execution status.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W 5 SRQ 0 R Description Slave Transmission Request Indicates whether or not the unit is in transmit request status as a slave unit. 1: The unit is in transmit request status as a slave unit [Setting condition] When the CMX flag is cleared to 0 after the slave transmit request command is issued.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W Description 2 ⎯ 0 R Reserved This bit is always read as 0. 1 RSS 0 R Receive Broadcast Bit Status Indicates the received broadcast bit value. This flag is valid when the slave/broadcast reception is started. (This flag is changed at the timing of setting the RxS flag in IERSR.) The previous value remains unchanged until the next slave/broadcast reception is started.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.18 IEBus Transmit/Runaway Status Register (IETSR) IETSR detects transmit data ready, transmit start, transmit normal completion, transmit completion with an error, or runaway states. Each status flags in IETSR corresponds to a bit in the IEBus transmit/runaway interrupt enable register (IEIET) that enables or disables each interrupt.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W 2 TxS 0 R/W Description Transmit Start Detection Indicates that the IEB starts transmission.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W Description 0 TxE 0 R/W Transmit Error Completion Indicates that data for the number of bytes specified by the message length bits is not completed and that the data transmission is terminated. The source of this error can be checked by the contents of IETEF. This flag is set at the timing that an error indicated by IETEF occurs.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.19 IEBus Transmit/Runaway Interrupt Enable Register (IEIET) IEIET enables/disables IETSR transmit ready, transmit start, transmit normal completion, transmit completion with an error, and runaway interrupts. Bit Bit Name Initial Value R/W 7 TxRDYE 0 R/W Description Transmit Data Ready Interrupt Enable Enables/disables a transmit data ready interrupt.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.20 IEBus Transmit Error Flag Register (IETEF) IETEF checks the source of a TxE interrupt indicated in IETSR. This register detects an overflow of a maximum number of bytes in one frame, arbitration loss, underrun error, timing error, and NAK reception. Initial Value R/W Description 7 to 5 ⎯ All 0 ⎯ Reserved 4 0 R/W Bit Bit Name These bits are always read as 0 and cannot be modified.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W Description Bit Bit Name Initial Value R/W Description 2 TTME 0 R/W Timing Error Set to 1 if data is not transmitted at the timing specified by the IEBus protocol during data transmission. The IEB sets the TxE flag and enters the wait state.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W 0 ACK 0 R/W Description Acknowledge bit Status Indicates the data received in the acknowledge bit of the data field. • Acknowledge bit other than in the data field The IEB terminates the transmission and enters the wait state if a NAK is received. In this case, this bit and the TxE flag are set to 1.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.21 IEBus Receive Status Register (IERSR) IERSR detects receive data ready, receive start, transmit/receive normal completion, or receive completion with an error. Each status flag in IERSR corresponds to a bit in the IEIER that enables/disables each interrupt. Bit Bit Name Initial Value R/W Description 7 RxRDY 1 R/W Receive Data Ready Indicates that the receive data is stored in IERBR and that the receive data can be read.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W Description 1 RxF 0 R/W Receive Normal Completion Indicates that data for the number of bytes specified by the message length bits has been received and with no error. [Setting condition] When data for the number of bytes specified by the message length bits has been received normally.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.3.22 IEBus Receive Interrupt Enable Register (IEIER) IEIER enables/disables IERSR reception ready, receive start, transmit/receive normal completion, and receive completion with an error interrupts. Bit Bit Name Initial Value R/W 7 RxRDYE 0 R/W Description Receive Data Ready Interrupt Enable Enables/disables a receive data ready interrupt.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name 7 to 4 ⎯ Initial Value R/W All 0 ⎯ Description Reserved These bits are always read as 0 and cannot be modified. 3 OVE 0 R/W Overrun Control Flag Used to control the overrun during data reception. The IEB sets the OVE and RxE flags when the IEB receives the next byte data while the receive data has not been read (the RxRDY flag is not cleared) and when the parity bit reception has been started.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Bit Bit Name Initial Value R/W Description 1 DLE 0 R/W Overflow of Maximum Number of Receive Bytes in One Frame Indicates that the maximum number of bytes defined by communications mode have been received because a parity error or overrun error occurred, or that the reception has not be completed because the message length value exceeds the maximum number of receive bytes in one frame. The IEB sets the RxE flag and enters the wait state.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.4 Operation Descriptions 14.4.1 Master Transmit Operation This section describes an example of master transmission using the DTC after slave reception. (1) IEB Initialization (a) Setting the IEBus Control Register (IECTR) Enable the IEBus pins, select the signal polarity, and select a clock supplied to the IEB. Clear the LUEE bit to 0 since the transfer is performed by the DTC.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Because the TxRDY flag is retained after a reset, the DTC transfer starts when the IETxI is enabled and the first data for the data field is written to IETBR. The DTC negates the TxRDY flag and the first byte of DTC transfer is completed. (3) Master Transmission Flow Figure 14.8 shows the master transmission flow. Numbers in the following description correspond to the number in figure 14.8. 1.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] H: Header, MA: Master address field, SA: Slave address field, CF: Control field, LF: Message length field, D1, D2,...
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] The above registers can be specified in any order. (The register specification order does not affect the IEB operation.) (2) DTC Initialization 1. Set the start address of the RAM which stores the register information necessary for the DTC transfer in the vector address (H'000004D2) to be accessed when a DTC transfer request is generated. 2. Specify the following from the start address of the RAM.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 3. When the first data is received, the RxRDY flag is set to 1. A DTC transfer request by IERxI occurs, and the DTC loads data from the IEBus receive buffer register (IERBR) and clears the RxRDY flag. 4. Similarly, the data field reception and load are repeated. 5. When the last data is received, the DTC completes the data transfer for the specified number of bytes after loading the receive data to the RAM.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] H: Header, MA: Master address field, SA: Slave address field, CF: Control field, LF: Message length field, D1, D2,...
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] H: Header, MA: Master address field, SA: Slave address field, CF: Control field, LF: Message length field, D1, D2,..., Dn-1, Dn: Data field Slave reception Dn Broadcast reception H MA SA CF LF D1 D2 Dn-1 Dn IECTR Broadcast reception is performed while the DEE bit is set to 1. RE, DEE IEFLG RSS IEFLG CMX MRQ SRQ SRE The RxRDY flag has not been cleared when the control field is received.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (c) Setting the IEBus Slave Address Setting Registers 1 and 2 (IESA1 and IESA2) Specify the communications destination slave unit address. (d) Setting the IEBus Master Control Register (IEMCR) Select broadcast/normal communications, specify the number of retransfer counts at arbitration loss, and specify the control bits. (e) Setting the IEBus Receive Interrupt Enable Register (IEIER) Enable the RxRDY (IERxI), RxS, RxF, and RxE (IERSI) interrupts.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (3) Master Reception Flow Figure 14.11 shows the master reception flow. Numbers in the following description correspond to the number in figure 14.11. In this example, the DTC is specified when the frame reception starts. 1. After the IEB has been initialized, a master communications request command is issued from IECMR.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] H: Header, MA: Master address field, SA: Slave address field, CF: Control field, LF: Message length field, D1, D2,...
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (c) Setting the IEBus Transmit Message Length Register (IETBFL) Specify the message length bits. (d) Setting the IEBus Transmit/Runaway Interrupt Enable Register (IEIET) Enable the TxRDY (IETxI), TxS, and TxE (IETSI) interrupts. The above registers can be specified in any order. (The register specification order does not affect the IEB operation.) (2) DTC Initialization 1.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] transfer request by IETxI is generated and the second byte data is written to the transmit buffer. 5. Similarly, the above data field load and transmission operations are repeated. 6. The DTC completes the data transfer for the number of specified bytes when data to be transmitted in the last byte is written to. At this time, the DTC does not clear the TxRDY flag.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] H: Header, MA: Master address field, SA: Slave address field, CF: Control field, LF: Message length field, D1, D2,...
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.5 Interrupt Sources Figures 14.13 and 14.14 show the transmit and receive interrupt sources, respectively. IETSR IETxI (TxRDY interrupt) IEIET TxRDY DTC TxRDYE IRA IRAE TxS CPU IETSI (Transmit status interrupt) TxSE IETEF TxF AL TxFE UE (*) TTME TxE TxEE RO ACK Note: * The TxE flag is set at the timing when an error source of IETEF occurs.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.6 Usage Notes 14.6.1 Setting Module Stop Mode The IEB is enabled or disabled by setting the module stop control register. In the initial state, the IEB is disabled. After the module stop mode is canceled, registers can be accessed. For details, see section 24, Power-Down Modes. 14.6.2 TxRDY Flag and Underrun Error 1. The TxRDY flag indicates that IETBR is empty. Writing to IETBR by the DTC clears the TxRDY flag.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.6.3 RxRDY Flag and Overrun Error 1. The RxRDY flag indicates that IERBR stores data. Reading from IERBR by the DTC clears the RxRDY flag. Meanwhile, the RxRDY flag must be cleared by software since reading from IERBR by the CPU does not clear the RxRDY flag. 2.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (4) RO Flag When retransfer is performed up to the maximum number of transfer bytes defined by the protocol because of reception of a NAK from the receive side during data field transmission, the number of transferred bytes may be less than that of bytes specified by the message length. At this time the RO flag is set. Moreover, when the value of the message length bits is greater than the maximum number of transfer bytes, the RO flag is also set.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] (3) DLE Flag When retransfer is performed up to the maximum number of transfer bytes defined by the protocol because of reception of a NAK caused by a parity or an overrun error during data field reception, the number of transferred bytes may be greater than that of bytes specified by the message length. At this time the DLE flag is set.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.6.7 Notes on DTC Specification When transmit or receive data is transferred by the DTC, bit 5 (for transmission) or bit 6 (for reception) in DTCERG must be set by the bit manipulation instruction (such as BSET or BCLR). In this case, other bits (bits 7 and 4 to 0) in DTCERG must not be set to 1. 14.6.8 Error Handling in Transmission Figure 14.15 shows the operation when a timing error occurs.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] 14.6.9 Power-Down Mode Operation The IEB stops operation and is initialized in power-down modes such as module stop, watch, software standby and hardware standby modes. To initialize the IEB, the module stop mode must be specified. To reduce power consumption during IEB operation, the sleep mode must be used. 14.6.10 Notes on Middle-Speed Mode In middle-speed mode, the IEB registers must not be read from or written to. 14.6.
Section 15 Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) This LSI has independent serial communication interfaces (SCIs). The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
Section 15 Serial Communication Interface (SCI) • Parity: Even, odd, or none • Receive error detection: Parity, overrun, and framing errors • Break detection: Break can be detected by reading the RxD pin level directly in the case of a framing error • Average transfer rate generator (SCI_0): 720 kbps, 460.784 kbps, or 115.192 kbps can be selected at 16-MHz operation (H8S/2239 Group only). • Transfer rate clock can be input from the TPU (SCI_0) (H8S/2239 Group only).
Section 15 Serial Communication Interface (SCI) Bus interface Figure 15.1 shows a block diagram of the SCI (except SCI_0 of the H8S/2239 Group), and figure 15.2 shows that of the SCI_0 of the H8S/2239 Group.
Bus interface Section 15 Serial Communication Interface (SCI) Module data bus RDR SCMR TDR Internal data bus BRR SSR φ SCR RxD0 RSR SMR TSR SEMR φ/16 φ/64 Transmission/ reception control TxD0 Clock Parity generation PG1/IRQ7 φ/4 Baud rate generator TEI TXI RXI ERI Parity check C/A CKE1 SSE Average transfer rate generator External clock SCK0 10.667-MHz operation 115.152 kbps 460.606 kbps 16-MHz operation 115.196 kbps 460.
Section 15 Serial Communication Interface (SCI) 15.2 Input/Output Pins Table 15.1 shows the pin configuration for each SCI channel. Table 15.
Section 15 Serial Communication Interface (SCI) • Serial status register (SSR) • Smart card mode register (SCMR) • Bit rate register (BRR) • Serial expansion mode register (SEMR0)* Note: * This register is in the channel 0 of the H8S/2239 Group only. 15.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically.
Section 15 Serial Communication Interface (SCI) 15.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 15.3.5 Serial Mode Register (SMR) SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus parity bit is even.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 15.3.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 6 BLK 0 R/W When this bit is set to 1, the SCI operates in block transfer mode. For details on block transfer mode, refer to section 15.7.3, Block Transfer Mode. 0: Normal smart card interface mode operation (initial value) • Error signal transmission, detection, and automatic data retransmission are performed. • The TXI interrupt is generated by the TEND flag. • The TEND flag is set 12.5 etu (11.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 3 BCP1 0 R/W Base Clock Pulse 0 and 1 2 BCP0 0 R/W These bits specify the number of base clock periods in a 1-bit transfer interval on the Smart Card interface. 00: 32 clock (S = 32) 01: 64 clock (S = 64) 10: 372 clock (S = 372) 11: 256 clock (S = 256) For details, refer to section 15.7.4, Receive Data Sampling Timing and Reception Margin. S stands for the value of S in BRR (see section 15.3.
Section 15 Serial Communication Interface (SCI) • Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0, or clearing the TIE bit to 0.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 0 and 1 0 CKE0 0 R/W Selects the clock source and SCK pin function. Asynchronous mode 00: On-chip baud rate generator SCK pin functions as I/O port 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK pin. 1×: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK pin.
Section 15 Serial Communication Interface (SCI) • Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0, or clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in Smart Card interface mode. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RERF, FER, and ORER flags in SSR, are not performed.
Section 15 Serial Communication Interface (SCI) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ between normal serial communication interface mode and Smart Card interface mode.
Section 15 Serial Communication Interface (SCI) Bit 5 Bit Name ORER Initial Value R/W Description 0 1 R/(W)* Overrun Error Indicates that an overrun error occurred during reception, causing abnormal termination. [Setting condition] When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1.
Section 15 Serial Communication Interface (SCI) Bit 3 Bit Name PER Initial Value R/W Description 0 1 R/(W)* Parity Error Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. [Setting condition] When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1.
Section 15 Serial Communication Interface (SCI) Notes: 1. Only a 0 can be written to this bit, to clear the flag. 2. Supported only by the H8S/2239 Group. 3. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. • Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name TDRE Initial Value R/W Description 1 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data.
Section 15 Serial Communication Interface (SCI) Bit 5 Bit Name ORER Initial Value R/W Description 0 1 R/(W)* Overrun Error Indicates that an overrun error occurred during reception, causing abnormal termination. [Setting condition] When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial cannot be continued while the ORER flag is set to 1.
Section 15 Serial Communication Interface (SCI) Bit 3 Bit Name PER Initial Value R/W Description 0 1 R/(W)* Parity Error Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. [Setting condition] When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W 2 TEND 1 R Description Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] • When the TE bit in SCR is 0 and the ERS bit is also 0 • When the ERS bit is 0 and the TDRE bit is 1 after the specified interval following transmission of 1-byte data.
Section 15 Serial Communication Interface (SCI) 15.3.8 Smart Card Mode Register (SCMR) SCMR is a register that selects Smart Card interface mode and its transfer format. Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved These bits are always read as 1, and cannot be modified. 3 SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format.
Section 15 Serial Communication Interface (SCI) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
Section 15 Serial Communication Interface (SCI) Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of base clock periods in a 1-bit transfer interval) can be selected. For details, refer to section 15.7.
Section 15 Serial Communication Interface (SCI) Operating Frequency φ (MHz) 3.6864* 4* 3 4.9152* 3 5* 3 3 Bit Rate 1 (bps)* n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.
Section 15 Serial Communication Interface (SCI) Operating Frequency φ (MHz) 9.8304* 3 10 12 12.288 Bit Rate 1 (bps)* n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.
Section 15 Serial Communication Interface (SCI) Operating Frequency φ (MHz) 18* 19.6608* 2 20* 2 2 Bit Rate 1 (bps)* n N Error (%) n N Error (%) n N Error (%) 110 3 79 –0.12 3 86 0.31 3 88 –0.25 150 2 233 0.16 2 255 0.00 3 64 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.
Section 15 Serial Communication Interface (SCI) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) N φ (MHz) Maximum Bit Rate (kbps) n N 0 0 2 9.8304* 307.2 0 0 0 0 10 312.5 0 0 0 0 12 375.0 0 0 0 0 384.0 0 0 Maximum Bit Rate (kbps) n φ (MHz) 2 2* 62.5 2 2.097152* 65.536 2 2.4576* 76.8 2 * 3 93.75 2 3.6864* 115.2 0 0 12.288 1 14* 437.5 0 0 4* 125.0 0 0 14.7456* 460.8 0 0 0 16* 500.0 0 0 537.6 0 0 2 4.9152* 2 5* 6* 2 2 153.
Section 15 Serial Communication Interface (SCI) Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (kbps) φ (MHz) 2* 0.5000 31.25 9.8304* 2 2 External Input Clock (MHz) Maximum Bit Rate (kbps) 2.4576 153.6 2 2.097152* 0.5243 2 2.4576* 0.6144 2 * 3 0.7500 32.768 10 2.5000 156.25 38.4 12 3.0000 187.5 46.875 192.0 0.9216 57.6 12.288 1 14* 3.0720 2 3.6864* 3.5000 218.75 4* 1.0000 62.5 14.7456* 3.
Section 15 Serial Communication Interface (SCI) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) 2* 4* 2 6* 2 Bit Rate (bps) n N n N 110 3 70 — — 250 2 124 2 500 1 249 1k 1 2.
Section 15 Serial Communication Interface (SCI) Operating Frequency φ (MHz) Bit Rate (bps) 16* 10 20* 1 n N n N 250 — — 3 249 500 — — 3 1k — — 2 1 n N 124 — — 249 — — 110 2.5 k 1 249 2 99 2 124 5k 1 124 1 199 1 249 10 k 0 249 1 99 1 124 25 k 0 99 0 159 0 199 50 k 0 49 0 79 0 99 100 k 0 24 0 39 0 49 250 k 0 9 0 15 0 19 500 k 0 4 0 7 0 9 0 3 0 4 0 0* 0 1 0 0* 1M 2.5 M 5M Legend: Blank: Cannot be set.
Section 15 Serial Communication Interface (SCI) Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372) Operating Frequency φ (MHz) 2 5.00* Bit Rate (bps) N Error (%) 6720 0 0.01 9600 0 30.00 2 7.00* N 7.1424* 2 10.00 10.7136 Error (%) N Error (%) N Error (%) N Error (%) 1 30.00 1 28.57 1 0.01 1 7.14 0 1.99 0 0.00 1 30.00 1 25.00 Operating Frequency φ (MHz) 14.2848* 1 16.00* 1 13.00 1 18.00* 1 20.
Section 15 Serial Communication Interface (SCI) 15.3.10 Serial Expansion Mode Register (SEMR_0) SEMR_0 is an 8-bit register that expands SCI_0 functions; such as setting of the base clock, selecting of the clock source, and automatic setting of the transfer rate. Note: Supported only by the H8S/2239 Group only.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 2 ACS2 0 R/W Asynchronous Clock Source Select 1 ACS1 0 R/W 0 ACS0 0 R/W When an average transfer rate is selected, the base clock is set automatically regardless of the ABCS value. Note that average transfer rates are not supported for operating frequencies other than 10.667 MHz and 16 MHz.
1 1 2 2 1 1 2 2 5 6 8 7 3 3 9 10 11 12 13 14 5 6 7 8 15 16 7 Average error = −0.043% Average transfer rate = 3.6848 MHz/8 = 460.606 kbps 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 1 bit = Base clock x 8* 3.6848 MHz 4 5 6 5.333 MHz 4 Average error = −0.043% Average transfer rate = 1.8424 MHz/16 = 115.
φ = 16 MHz 1 1 3 3 4 5 4 Rev. 6.00 Mar. 18, 2010 Page 584 of 982 REJ09B0054-0600 1 1 Figure 15.4 Example of the Internal Base Clock When the Average Transfer Rate Is Selected (2) 1 1 8 1 bit = Base clock x 16* 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 3 3 4 5 4 6 7 8 9 10 11 12 13 14 15 16 7 5.
Section 15 Serial Communication Interface (SCI) 15.4 Operation in Asynchronous Mode Figure 15.5 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Section 15 Serial Communication Interface (SCI) Table 15.
Section 15 Serial Communication Interface (SCI) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the base clock as shown in figure 15.6.
Section 15 Serial Communication Interface (SCI) 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Note: Example for H8S/2239 Group with the ABCS bit in SEMR_0 set to a value other than 1. When ABCS is set to 1, the clock frequency is 8 times the bit rate and sampling of received data takes place at the fourth rising edge of the basic clock. Figure 15.6 Receive Data Sampling Timing in Asynchronous Mode 15.
Section 15 Serial Communication Interface (SCI) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in figure 15.8. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Section 15 Serial Communication Interface (SCI) 15.4.5 Serial Data Transmission (Asynchronous Mode) Figure 15.9 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Section 15 Serial Communication Interface (SCI) Figure 15.10 shows a sample flowchart for data transmission. [1] Initialization Start transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.11 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 15 Serial Communication Interface (SCI) Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.12 shows a sample flow chart for serial data reception. Table 15.
Section 15 Serial Communication Interface (SCI) Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure Yes that the ORER, PER, and FER flags are PER ∨ FER ∨ ORER = 1 all cleared to 0.
Section 15 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 15.12 Sample Serial Reception Data Flowchart (2) Rev. 6.00 Mar.
Section 15 Serial Communication Interface (SCI) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 15 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = Data transmission to receiving station receiving station specified by ID specification Legend: MPB: Multiprocessor bit Figure 15.
Section 15 Serial Communication Interface (SCI) [1] Initialization Start transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI) 15.5.2 Multiprocessor Serial Data Reception Figure 15.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.
Section 15 Serial Communication Interface (SCI) Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Start reception Set MPIE bit in SCR to 1 [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
Section 15 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 6.00 Mar.
Section 15 Serial Communication Interface (SCI) 15.6 Operation in Clocked Synchronous Mode Figure 15.17 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronous with the rising edge of the serial clock.
Section 15 Serial Communication Interface (SCI) Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Clear TE and RE bits in SCR to 0 [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [2] Set value in BRR [3] [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used.
Section 15 Serial Communication Interface (SCI) 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6.
Section 15 Serial Communication Interface (SCI) [1] Initialization Start transmission Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin.
Section 15 Serial Communication Interface (SCI) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.21 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in RSR. 2.
Section 15 Serial Communication Interface (SCI) Initialization [1] Start reception [2] Read ORER flag in SSR Yes ORER = 1 [3] No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Section 15 Serial Communication Interface (SCI) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.23 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations.
Section 15 Serial Communication Interface (SCI) Initialization [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI) 15.7 Operation in Smart Card Interface The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface mode is carried out by means of a register setting. 15.7.1 Pin Connection Example Figure 15.24 shows an example of connection with the Smart Card.
Section 15 Serial Communication Interface (SCI) When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 DE Transmitting station output Legend: Ds: D7 to D0: Dp: DE: Receiving station output Start bit Data bits Parity bit Error signal Figure 15.
Section 15 Serial Communication Interface (SCI) state Z. In this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O/E bit in SMR to 1 to invert the parity bit for both transmission and reception. 15.7.3 Block Transfer Mode Operation in block transfer mode is the same as that in the normal Smart Card interface mode, except for the following points. • In reception, though the parity check is performed, no error signal is output even if an error is detected.
Section 15 Serial Communication Interface (SCI) M = (0.5 – 1/2 × 372) × 100% = 49.866% 372 clocks 186 clocks 0 185 185 371 0 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15.28 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) 15.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below.
Section 15 Serial Communication Interface (SCI) after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to 1. Whether SCI has finished transmission or not can be checked with the TEND flag. 15.7.
Section 15 Serial Communication Interface (SCI) nth transfer frame Transfer frame n + 1st Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR from TDR TEND FER/ERS Figure 15.29 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 15.30.
Section 15 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 15.31 Example of Transmission Processing Flow Rev. 6.00 Mar.
Section 15 Serial Communication Interface (SCI) 15.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 15.32 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1.
Section 15 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0 No Yes Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 15.33 Example of Reception Processing Flow 15.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Section 15 Serial Communication Interface (SCI) When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. Powering On: To secure clock duty from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2.
Section 15 Serial Communication Interface (SCI) 15.8 SCI Select Function (H8S/2239 Group Only) SCI_0 provides the SCI select function that enables one-to-one clocked synchronous communication between a master LSI and multiple slave LSIs (these LSIs). Figure 15.36 shows an example of communication using the SCI select function and figure 15.37 shows the summary of its operation. The master LSI enables to communicate with the slave LSI_A by setting the SEL_A signal to low and the SEL_B signal to high.
Section 15 Serial Communication Interface (SCI) Master LSI [Master LSI] Master LSI Salve LSI_A communication Salve LSI_B communication M_SCK M_TxD D0 D1 D7 D0 D1 D7 M_RxD D0 D1 D7 D0 D1 D7 SEL_A SEL_B [Salve LSI_A] IRQ7 (SEL_A) SCK0_A Fixed high RSR0_A TxD0_A D0 Hi-Z D6 D0 D1 D7 Hi-Z D7 [Salve LSI_B] IRQ7 (SEL_B) SCK0_B Fixed high RSR0_B TxD0_B D0 Hi-Z D0 D6 D1 D7 D7 Hi-Z Figure 15.37 Summary of SCI Select Function Operation Rev. 6.00 Mar.
Section 15 Serial Communication Interface (SCI) 15.9 Interrupt Sources 15.9.1 Interrupts in Normal Serial Communication Interface Mode Table 15.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
Section 15 Serial Communication Interface (SCI) Table 15.
Section 15 Serial Communication Interface (SCI) 15.9.2 Interrupts in Smart Card Interface Mode Table 15.13 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Note: In case of block transfer mode, see section 15.9.1, Interrupts in Normal Serial Communication Interface Mode. Table 15.
Section 15 Serial Communication Interface (SCI) 15.10 Usage Notes 15.10.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 15.10.
Section 15 Serial Communication Interface (SCI) 15.10.5 Restrictions on Use of DMAC* or DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after the TDR is updated by the DMAC* or the DTC. Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated (figure 15.38).
Section 15 Serial Communication Interface (SCI) TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 15.39 shows a sample flowchart for mode transition during transmission. Port pin states are shown in figures 15.40 and 15.41.
Section 15 Serial Communication Interface (SCI) End of transmission Start of transmission Exit from software standby Transition to software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Start Port Stop Port input/output Port SCI TxD output High output SCI TxD output Figure 15.
Section 15 Serial Communication Interface (SCI) • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception.
Section 15 Serial Communication Interface (SCI) 15.10.7 Switching from SCK Pin Function to Port Pin Function • Problem in Operation When switching the SCK pin function to the output port function (high-level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0… Switchover to port output 4.
Section 15 Serial Communication Interface (SCI) High-level output SCK/port 1. End of transmission Data TE Bit 6 Bit 7 2. TE = 0 4. C/A = 0 C/A 3. CKE1 = 1 CKE1 5. CKE1 = 0 CKE0 Figure 15.44 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) 15.10.8 Assignment and Selection of Registers Some serial communication interface registers are assigned to the same address as other registers.
Section 15 Serial Communication Interface (SCI) Rev. 6.00 Mar.
2 Section 16 I C Bus Interface (IIC) (Option) 2 Section 16 I C Bus Interface (IIC) (Option) 2 An I C bus interface is available as an option. Observe the following notes when using this option. 1. For masked ROM versions, a W is added to the part number in products in which this optional function is used. Examples: HD6432239WTE 2 The H8S/2258 Group, H8S/2239 Group, and H8S/2238 Group have an internal I C bus interface of two channels.
2 Section 16 I C Bus Interface (IIC) (Option) • Wait function in slave mode A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible.
2 Section 16 I C Bus Interface (IIC) (Option) φ PS ICCR SCL Clock control Noise canceler Bus state decision circuit SDA ICSR Arbitration decision circuit ICDRT Output data control circuit ICDRS Internal data bus ICMR ICDRR Noise canceler Address comparator SAR, SARX Legend: ICCR: ICMR: ICSR: ICDR: SAR: SARX: PS: Interrupt generator I2C bus control register I2C bus mode register I2C bus status register I2C bus data register Slave address register Second slave address register Prescaler Int
2 Section 16 I C Bus Interface (IIC) (Option) VDD VCC SCL SCL SDA SDA SCL in SDA in SCL SDA SDA out (Master) SCL in This LSI SCL out SCL out SDA in SDA in SDA out SDA out SCL in (Slave 1) SCL SDA SCL out (Slave 2) 2 Figure 16.2 I C Bus Interface Connections (Example: This LSI as Master) 16.2 Input/Output Pins 2 Table 16.1 shows the pin configuration for the I C bus interface. Table 16.
2 Section 16 I C Bus Interface (IIC) (Option) ICE is 1. For details on the module stop control register, refer to section 24.1.2, Module Stop Control Registers A to C (MSTPCRA to MSTPCRC).
2 Section 16 I C Bus Interface (IIC) (Option) when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. ICDR can be written and read only when the ICE bit is set to 1 in ICCR. The value of ICDR is undefined after a reset. The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the TDRE and RDRF flags affects the status of the interrupt flags.
2 Section 16 I C Bus Interface (IIC) (Option) 16.3.2 Slave Address Register (SAR) SAR selects the slave address and selects the transfer format. SAR can be written and read only when the ICE bit is cleared to 0 in ICCR. Bit Bit Name Initial Value R/W Description 7 SVA6 0 R/W Slave Address 6 to 0 6 SVA5 0 R/W Sets a slave address. 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W 16.3.
2 Section 16 I C Bus Interface (IIC) (Option) Table 16.2 Transfer Format SAR SARX FS FSX I C Transfer Format 0 0 SAR and SARX are used as the slave addresses with the I C bus format. 0 1 Only SAR is used as the slave address with the I C bus format. 1 0 Only SARX is used as the slave address with the I C bus format. 1 1 Clock synchronous serial format (SAR and SARX are invalid) 16.3.4 2 2 2 2 2 I C Bus Mode Register (ICMR) ICMR sets the transfer format and transfer rate.
2 Section 16 I C Bus Interface (IIC) (Option) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. 2 With the I C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low.
2 Section 16 I C Bus Interface (IIC) (Option) 2 Table 16.3 I C Transfer Rate SCRX ICMR Bit 5 and 6 Bit 5 Bit 4 Bit 3 Transfer Rate IICX CKS2 CKS1 CKS0 Clock φ = 5 MHz* φ = 8 MHz* φ = 10 MHz φ = 16 MHz*2 φ = 20 MHz*2 0 0 0 0 φ/28 179 MHz 286 kHz 357 kHz 571 kHz*1 714 kHz*1 0 0 0 1 φ/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz*1 0 0 1 0 φ/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz*1 0 0 1 1 φ/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 0 1 0 0 φ/80 62.
2 Section 16 I C Bus Interface (IIC) (Option) 16.3.5 Serial Control Register X (SCRX) SCRX controls the IIC operating modes. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved The initial value should not be changed. 2 6 IICX1 0 R/W I C Transfer Rate Select 1 and 0 5 IICX0 0 R/W Selects the transfer rate in master mode, together with bits CKS2 to CKS0 in ICMR. Refer to table 16.3. IICX1 controls IIC_1 and IICX0 controls IIC_0.
2 Section 16 I C Bus Interface (IIC) (Option) 16.3.6 2 I C Bus Control Register (ICCR) 2 2 I C bus control register (ICCR) consists of the control bits and interrupt request flags of I C bus interface. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I C Bus Interface Enable 2 2 When this bit is set to 1, the I C bus interface module is enabled to send/receive data and drive the bus since it is connected to the SCL and SDA pins. ICMR and ICDR can be accessed.
2 Section 16 I C Bus Interface (IIC) (Option) Bit Bit Name Initial Value R/W 3 ACKE 0 R/W Description Acknowledge Bit Judgement Selection 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. 1: If the acknowledge bit is 1, continuous transfer is interrupted. In this LSI, the DTC can be used to perform continuous transfer.
2 Section 16 I C Bus Interface (IIC) (Option) Bit Bit Name Initial Value R/W Description 1 IRIC 0 R/W I C Bus Interface Interrupt Request Flag Also see table 16.4.
2 Section 16 I C Bus Interface (IIC) (Option) Bit Bit Name Initial Value R/W 0 SCP 1 W Description Start Condition/Stop Condition Prohibit bit The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored.
2 Section 16 I C Bus Interface (IIC) (Option) Table 16.
2 Section 16 I C Bus Interface (IIC) (Option) 16.3.7 2 I C Bus Status Register (ICSR) ICSR consists of status flags. Bit 7 Bit Name ESTP Initial Value 0 R/W Description R/(W)* Error Stop Condition Detection Flag 2 This bit is valid in I C bus format slave mode.
2 Section 16 I C Bus Interface (IIC) (Option) Bit 4 Bit Name AASX Initial Value R/W 0 R/(W)* Second Slave Address Recognition Flag Description [Setting condition] When the second slave address is detected in slave receive mode and FSX = 0 [Clearing conditions] 3 AL 0 • When 0 is written in AASX after reading AASX = 1 • When a start condition is detected • In master mode * R/(W) Arbitration Lost Flag Indicates that bus arbitration was lost in master mode.
2 Section 16 I C Bus Interface (IIC) (Option) Bit 1 Bit Name ADZ Initial Value R/W 0 R/(W)* General Call Address Recognition Flag Description 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00).
2 Section 16 I C Bus Interface (IIC) (Option) Bit Bit Name Initial Value R/W 0 ACKB 0 R/W Description Acknowledge Bit Stores acknowledge data.
2 Section 16 I C Bus Interface (IIC) (Option) 16.3.8 DDC Switch Register (DDCSWR) 2 DDCSWR controls the I C bus interface format automatic switching function and internal latch clear. Bit Bit Name 7 to 4 ⎯ Initial Value R/W All 0 R/(W)* Reserved Description The write value should always be 0.
2 Section 16 I C Bus Interface (IIC) (Option) (a) I2C bus format (FS = 0 or FSX = 0) S SLA R/W A DATA A A/A P 1 7 1 1 n 1 1 1 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m ≥ 1) m (b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0) S SLA R/W A DATA A/A S SLA R/W A DATA A/A P 1 7 1 1 n1 1 1 7 1 1 n2 1 1 1 m1 1 m2 n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 ≥ 1) 2 2 Figure
2 Section 16 I C Bus Interface (IIC) (Option) 16.4.2 Initial Setting At startup the following procedure is used to initialize the IIC. Start initialization Set MSTPB4 = 0 (IIC0) MSTPB3 = 0 (IIC1) (MSTPCRB) Set IICE = 1 (SCRX) Clear module stop. Enable CPU access by IIC control register and data register. Set ICE = 0 (ICCR) Enable SAR and SARX access. Set SAR and SARX Set transfer format for 1st slave address, 2nd slave address, and IIC (SVA8 to SVA0, FS, SVAX6 to SVAX0, FSX).
2 Section 16 I C Bus Interface (IIC) (Option) Figure 16.7 is a flowchart showing an example of the master transmit mode. Start [1] Initial settings. Initial settings Read BBSY flag in ICCR [2] Determine status of SCL and SDA lines. No BBSY = 0? Yes Set MST = 1 and TRS = 1 (ICCR) [3] Set to master transmit mode. Write BBSY = 1 and SCP = 0 (ICCR) [4] Generate start condition. Read IRIC flag in ICCR [5] Wait for start condition to be met.
2 Section 16 I C Bus Interface (IIC) (Option) The procedure for transmitting data sequentially, synchronized with ICDR (ICDRT) write operations, is described below. [1] Perform initial settings as described in section 16.4.2, Initial Setting. [2] Read the BBSY flag in ICCR to confirm that the bus is free. [3] Set bits MST and TSR in ICCR to 1 to switch to the master transmit mode. [4] Write 1 to BBSY and 0 to SCP in ICCR.
2 Section 16 I C Bus Interface (IIC) (Option) Generate start condition SCL (Master output) 1 2 3 4 5 6 7 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Slave address 8 9 Bit 0 2 Bit 7 R/W SDA (Slave output) 1 Bit 6 Data 1 [7] A [5] Interrupt request IRIC Interrupt request IRTR ICDRT Data 1 Address + R/W ICDRS Data 1 Address + R/W Note: Do not write data to ICDR.
2 Section 16 I C Bus Interface (IIC) (Option) 16.4.4 Master Receive Operation 2 In I C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits the data containing the slave address + R/W (0: read) in the 1st frame after a start condition is generated in the master transmit mode. After the slave device is selected the switch to receive operation takes place.
2 Section 16 I C Bus Interface (IIC) (Option) Master receive mode Set TRS = 0 (ICCR) [1] Set to receive mode. Set ACKB = 0 (ICSR) Clear IRIC flag in ICCR Set WAIT = 1 (ICMR) Read ICDR [2] Receive start, dummy read. Read IRIC flag in ICCR No [3] Receive wait state (IRIC set at falling edge of 8th clock cycle) or Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle). IRIC = 1? Yes No [4] Data receive completed judgment.
2 Section 16 I C Bus Interface (IIC) (Option) Master receive mode Set TRS = 0 (ICCR) Set ACKB = 0 (ICSR) [1] Set to receive mode [2] Receive start, dummy read. [3] Receive wait state (IRIC set at falling edge of 8th clock cycle) Set ACKB = 1 (ICSR) [7] Set acknowledge data for final receive. Set TRS = 1 (ICCR) [9] Set TRS to generate stop condition.
2 Section 16 I C Bus Interface (IIC) (Option) [1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0, then set the WAIT bit in ICMR to 1. [2] When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. [3] The IRIC flag is set to 1 by the following two conditions.
2 Section 16 I C Bus Interface (IIC) (Option) (1) The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame. SCL is automatically held low, in synchronization with the internal clock, until the IRIC flag is cleared. (2) The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame. The IRTR flag is set to 1, indicating that reception of 1 frame of data has ended. The master device continues to output the receive clock for the receive data.
2 Section 16 I C Bus Interface (IIC) (Option) [8] 1 clock cycle wait time SCL (master output) 8 9 SDA Bit 0 (slave output) Data 2 [3] SDA (master output) 1 2 3 Stop condition generated 4 5 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Data 3 [3] 7 8 9 Bit 1 Bit 0 [12] [12] A A IRIC IRTR [4] IRTR = 0 ICDR [4] IRTR = 1 Data 1 User processing [13] IRTR = 0 Data 2 Data 3 [11] IRIC clearance [6] IRIC clearance [13] IRTR = 1 [10] ICDR read (data 2) [9] TRS set to 1 [7] ACKB set to 1 [14] I
2 Section 16 I C Bus Interface (IIC) (Option) Start Initialize Set MST = 0 and TRS = 0 in ICCR [1] Set ACKB = 0 in ICSR Read IRIC in ICCR No [2] IRIC = 1? Yes Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? No General call address processing * Description omitted Yes Read TRS in ICCR No TRS = 0? Slave transmit mode Yes Last receive? No Read ICDR Yes [3] [1] Select slave receive mode. Clear IRIC in ICCR [2] Wait for the first byte to be received (slave address).
2 Section 16 I C Bus Interface (IIC) (Option) The reception procedure and operations in slave receive mode are described below. [1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. [2] When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1.
2 Section 16 I C Bus Interface (IIC) (Option) Start condition issuance SCL (master output) 1 2 3 4 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 6 7 8 Bit 2 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 SCL (slave output) SDA (master output) SDA (slave output) Slave address R/W Data 1 [4] A RDRF IRIC ICDRS Address + R/W ICDRR Address + R/W User processing [5] ICDR read [5] IRIC clearance Figure 16.15 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) Rev. 6.00 Mar.
2 Section 16 I C Bus Interface (IIC) (Option) SCL (master output) 7 8 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (slave output) SDA (master output) Data 1 SDA (slave output) [4] [4] Data 2 A A RDRF IRIC ICDRS Data 1 ICDRR Data 1 User processing Data 2 [5] ICDR read [5] IRIC clearance Figure 16.16 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) Rev. 6.00 Mar.
2 Section 16 I C Bus Interface (IIC) (Option) 16.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 16.17 shows the sample flowchart for the operations in slave transmit mode.
2 Section 16 I C Bus Interface (IIC) (Option) In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. When making initial settings for slave receive mode, set the ACKE bit in ICCR to 1.
2 Section 16 I C Bus Interface (IIC) (Option) 6. Clear the IRIC flag to 0. 7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in the ACKB bit to 0. 8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode. 9. Dummy-read ICDR to release SCL on the slave side. 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1.
2 Section 16 I C Bus Interface (IIC) (Option) 16.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 16.19 shows the IRIC set timing and SCL control.
2 Section 16 I C Bus Interface (IIC) (Option) 16.4.8 Operation Using the DTC 2 The I C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction CPU processing by means of interrupts. Table 16.5 shows some example of processing using the DTC.
2 Section 16 I C Bus Interface (IIC) (Option) 16.4.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.20 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
2 Section 16 I C Bus Interface (IIC) (Option) The following items are not initialized: • Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, and STCR) • Internal latches used to retain register read information for setting/clearing flags in the ICMR, ICCR, ICSR, and DDCSWR registers • The value of the ICMR register bit counter (BC2 to BC0) • Generated interrupt sources (interrupt sources transferred to the interrupt controller) Notes on Initialization: • Interrupt flags and interrupt source
2 Section 16 I C Bus Interface (IIC) (Option) 16.5 Interrupt Source IICI is the interrupt source of IIC. Table 16.6 shows each interrupt source and its priority. The ICCR interrupt enable bit sets each interrupt and the setting is independently sent to the interrupt controller. Table 16.
2 Section 16 I C Bus Interface (IIC) (Option) 2 Table 16.7 I C Bus Timing (SCL and SDA Output) Item Symbol Output Timing Unit Notes SCL output cycle time tSCLO 28 tcyc to 256 tcyc ns Figure 27.34 SCL output high pulse width tSCLHO 0.5 tSCLO ns SCL output low pulse width tSCLLO 0.5 tSCLO ns SDA output bus free time tBUFO 0.5 tSCLO – 1 tcyc ns Start condition output hold time tSTAHO 0.
2 Section 16 I C Bus Interface (IIC) (Option) Table 16.8 Permissible SCL Rise Time (tsr) Values Time Indication 2 tcyc IICX Indication 0 7.5 tcyc Normal mode I C Bus Specification (Max) φ= 2 5 MHz* φ= 2 8 MHz* φ= 10 MHz φ= φ= 1 1 16 MHz* 20 MHz* 1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns 300 ns 300 ns 300 ns 300 ns 300 ns High-speed mode300 ns 1 17.
2 Section 16 I C Bus Interface (IIC) (Option) 2 Table 16.9 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] 2 Item tcyc Indication tSCLHO 0.5tSCLO (–tSr) tSCLLO 0.5tSCLO (–tSf ) tBUFO 0.
2 Section 16 I C Bus Interface (IIC) (Option) 6. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is 6tcyc. 7. The H8S/2258 Group is out of operation. 7. Note on ICDR Read at End of Master Reception To halt reception after completion of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes the SDA pin from low to high when the SCL pin is high, and generates the stop condition.
2 Section 16 I C Bus Interface (IIC) (Option) 8. Notes on Start Condition Issuance for Retransmission Depending on the timing combination with the start condition issuance and the subsequently writing data to ICDR, it may not be possible to issue the retransmission and the data transmission after retransmission condition issuance. After start condition issuance is done and determined the start condition, write the transmit data to ICDR, as shown below. Figure 16.
2 Section 16 I C Bus Interface (IIC) (Option) 2 9. Notes on I C Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, issue the stop condition instruction after reading SCL and determining it to be low, as shown below.
2 Section 16 I C Bus Interface (IIC) (Option) 11. Notes on ICDR Reads and ICCR Access in Slave Transmit Mode 2 In a transmit operation in the slave mode of the I C bus interface, do not read the ICDR register or read or write to the ICCR register during the period indicated by the shaded portion in figure 16.25.
2 Section 16 I C Bus Interface (IIC) (Option) 12. Notes on TRS Bit Setting in Slave Mode From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 16.26) 2 in the slave mode of the I C bus interface, the value set in the TRS bit in the ICCR register is effective immediately. However, at other times (indicated as (b) in figure 16.
2 Section 16 I C Bus Interface (IIC) (Option) 13. Notes on ICDR Reads in Transmit Mode and ICDR Writes in Receive Mode When attempting to read ICDR in the transmit mode (TRS = 1) or write to ICDR in the receive mode (TRS = 0) under certain conditions, the SCL pin may not be held low after the completion of the transmit or receive operation and a clock may not be output to the SCL bus line before the ICDR register access operation can take place properly.
2 Section 16 I C Bus Interface (IIC) (Option) • Arbitration is lost • The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A Transmit data does not match DATA2 A DATA3 A Data contention I 2C bus interface (Slave receive mode) S SLA R/W A • Receive address is ignored SLA R/W A DATA4 A • Automatically transferred to slave receive mode • Receive data is reco
2 Section 16 I C Bus Interface (IIC) (Option) SDA A SCL 9 BC2 to BC0 0 Transmit data 1 2 7 3 6 4 5 5 4 A 6 3 7 2 1 Confirm 8 SCL = L Transmit data 9 0 1 2 7 IRIC clear IRIC (sampling example) IRIC flag can be cleared 3 6 5 IRIC clear when BC2 to BC0 ≥ 2 IRIC flag can be cleared IRIC flag can not be cleared Figure 16.28 IRIC Flag Clearing Timing in Wait Operation 17.
2 Section 16 I C Bus Interface (IIC) (Option) Rev. 6.00 Mar.
Section 17 A/D Converter Section 17 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. A block diagram of the A/D converter is shown in figure 17.1. 17.1 Features • 10-bit resolution • Eight input channels • Conversion time: 9.6 µs per channel (at 13.
Section 17 A/D Converter Module data bus Bus interface ADCR ADCSR ADDRD ADDRB ADDRA ADDRC 10-bit D/A Successive approximations register AVCC Vref Internal data bus Off during A/D conversion wait time, on during A/D conversion.
Section 17 A/D Converter 17.2 Input/Output Pins Table 17.1 summarizes the input pins used by the A/D converter. The eight analog input pins are divided into two groups each of which consists of four channels; analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. Table 17.
Section 17 A/D Converter 17.3 Register Descriptions The A/D converter has the following registers. For details on the module stop control register, refer to section 24.1.2, Module Stop Control Registers A to C (MSTPCRA to MSTPCRC). • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D control/status register (ADCSR) • A/D control register (ADCR) 17.3.
Section 17 A/D Converter 17.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Bit Name Initial Value R/W Description 7 ADF 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
Section 17 A/D Converter Bit Bit Name Initial Value R/W 4 SCAN 0 R/W Description Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. Only set the SCAN bit while conversion is stopped (ADST = 0). 0: Single mode 1: Scan mode 3 ⎯ 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W Select analog input channels.
Section 17 A/D Converter 17.3.3 A/D Control Register (ADCR) The ADCR enables A/D conversion started by an external trigger signal. Initial Value Bit Bit Name 7 TRGS1 6 TRGS0 R/W Description 0 R/W Timer Trigger Select 1 and 0 0 R/W Enables the start of A/D conversion by a trigger signal. Only set bits TRGS0 and TRGS1 while conversion is stopped (ADST = 0).
Section 17 A/D Converter 17.4 Interface to Bus Master ADDRA to ADDRD are 16-bit registers. As the data bus to the bus master is 8 bits wide, the bus master accesses to the upper byte of the registers directly while to the lower byte of the registers via the temporary register (TEMP). Data in ADDR is read in the following way: When the upper-byte data is read, the upper-byte data will be transferred to the CPU and the lower-byte data will be transferred to TEMP.
Section 17 A/D Converter 17.5 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 17.5.
Section 17 A/D Converter Set* ADIE A/D conversion start Set* Set* ADST Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 Idle A/D conversion 2 Idle ADDRA Read conversion result* A/D conversion result 1 ADDRB Read conversion result* A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows indicate instructions executed by software. Figure 17.
Section 17 A/D Converter Continuous A/D conversion Clear*1 Set*1 ADST Clear*1 ADF State of channel 0 (AN0) A/D conversion time Idle A/D conversion 1 State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) ADDRA Idle Idle A/D conversion 4 Idle A/D conversion 2 A/D conversion 5* 2 Idle Idle A/D conversion 3 Idle A/D conversion result 1 ADDRB A/D conversion result 4 A/D conversion result 2 ADDRC A/D conversion result 3 ADDRD Notes: 1.
Section 17 A/D Converter (1) φ Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time Figure 17.5 A/D Conversion Timing Table 17.
Section 17 A/D Converter 17.5.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 17.6 shows the timing.
Section 17 A/D Converter 17.7 A/D Conversion Accuracy Definitions This LSI’s A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes. • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.7).
Section 17 A/D Converter Digital output 111 Ideal A/D conversion characteristic 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 17.7 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 17.8 A/D Conversion Accuracy Definitions Rev. 6.00 Mar.
Section 17 A/D Converter 17.8 17.8.1 Usage Notes Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 17.8.
Section 17 A/D Converter 17.8.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤ ANn ≤ AVcc. • Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open.
Section 17 A/D Converter AVCC Vref Rin*2 *1 100 Ω AN0 to AN7 *1 0.1 μF AVSS Notes: Values are reference values. 1. 10 μF 0.01 μF 2. Rin: Input impedance Figure 17.10 Example of Analog Input Protection Circuit Table 17.6 Analog Pin Specifications Item Min Max Unit Analog input capacitance — 20 pF Permissible signal source impedance — 5 kΩ 10 kΩ AN0 to AN7 To A/D converter 20 pF Note: Values are reference values. Figure 17.11 Analog Input Pin Equivalent Circuit Rev. 6.00 Mar.
Section 18 D/A Converter Section 18 D/A Converter 18.1 Features • 8-bit resolution • Two output channels • Conversion time: 10 µs, maximum (when load capacitance is 20 pF) • Output voltage: 0 V to Vref • Module stop mode can be set Note: The D/A converter is not included in the H8S/2227 Group.
Section 18 D/A Converter 18.2 Input/Output Pins Table 18.1 shows the pin configuration for the D/A converter. Table 18.
Section 18 D/A Converter 18.3.2 D/A Control Register (DACR) DACR controls D/A converter operation.
Section 18 D/A Converter 18.4 Operation Two channels of the D/A converter can perform conversion individually. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and the conversion results are output. An example of D/A conversion of channel 0 is shown below. The operation timing is shown in figure 18.2. 1. Write conversion data to DADR0. 2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts.
Section 18 D/A Converter 18.5 18.5.1 Usage Notes Analog Power Supply Current in Power-Down Mode If this LSI enters a power-down mode such as software standby, watch, subactive, subsleep, and module stop modes while D/A conversion is enabled, the D/A cannot retain analog outputs within the given D/A absolute accuracy* although it retains digital values. The analog power supply current is approximately the same as that during D/A conversion.
Section 18 D/A Converter Rev. 6.00 Mar.
Section 19 RAM Section 19 RAM The H8S/2239 has 32 kbytes of on-chip high-speed static RAM. The H8S/2258, H8S/2238B, H8S/2238R, H8S/2237, and H8S/2227 have 16 kbytes of on-chip high-speed static RAM. The H8S/2256, H8S/2236B, H8S/2236R have 8 kbytes of on-chip high-speed static RAM. The H8S/2235, H8S/2233, H8S/2225, H8S/2224, and H8S/2223 have 4 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data.
Section 19 RAM Rev. 6.00 Mar.
Section 20 Flash Memory (F-ZTAT Version) Section 20 Flash Memory (F-ZTAT Version) The features of the flash memory are summarized below. The block diagram of the flash memory is shown in figure 20.1. 20.1 Features • Capacity H8S/2239: 384 kbytes H8S/2258: 256 kbytes H8S/2238B: 256 kbytes H8S/2238R: 256 kbytes H8S/2227: 128 kbytes • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Section 20 Flash Memory (F-ZTAT Version) • Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. • Emulation function for flash memory in RAM The real-time emulation for programming of flash memory is possible by overlapping the flash memory to a part of RAM.
Section 20 Flash Memory (F-ZTAT Version) The differences between boot mode and user program mode are shown in table 20.1. Figure 20.3 shows the operation flow for boot mode and figure 20.4 shows that for user program mode.
Section 20 Flash Memory (F-ZTAT Version) 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication.
Section 20 Flash Memory (F-ZTAT Version) 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. 2.
Section 20 Flash Memory (F-ZTAT Version) 20.3 Block Configuration Figure 20.5 shows the block configuration of 384-kbyte flash memory. Figure 20.6 shows the block configuration of 256-kbyte flash memory. Figure 20.7 shows the block configuration of 128-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 384-kbyte flash memory is divided into 4 kbytes (8 blocks), 32 kbytes (1 block), and 64 kbytes (5 blocks).
Section 20 Flash Memory (F-ZTAT Version) EB0 Erase unit 4 kbytes H'000000 H'000001 H'000002 Programming unit: 128 bytes EB1 Erase unit 4 kbytes H'001000 H'001001 H'001002 Programming unit: 128 bytes EB2 Erase unit 4 kbytes H'002000 H'002001 H'002002 Programming unit: 128 bytes EB3 Erase unit 4 kbytes H'003000 H'003001 H'003002 Programming unit: 128 bytes H'00007F H'000FFF H'00107F H'001FFF H'00207F H'002FFF H'00307F H'003FFF EB4 Erase unit 4 kbytes H'004000 H'004001 H'004002 Progra
Section 20 Flash Memory (F-ZTAT Version) EB0 Erase unit 4 kbytes H'000000 H'000001 H'000002 Programming unit: 128 bytes EB1 Erase unit 4 kbytes H'001000 H'001001 H'001002 Programming unit: 128 bytes H'00007F H'000FFF H'001FFF EB2 Erase unit 4 kbytes H'002000 H'002001 H'002002 Programming unit: 128 bytes EB3 Erase unit 4 kbytes H'003000 H'003001 H'003002 Programming unit: 128 bytes H'004002 Programming unit: 128 bytes EB4 Erase unit 4 kbytes H'00107F H'00207F H'002FFF H'00307F H'00
Section 20 Flash Memory (F-ZTAT Version) EB0 Erase unit 1 kbyte H'000000 H'000001 H'000002 H'000380 H'000381 H'000382 EB1 Erase unit 1 kbyte H'000400 H'000401 H'000402 H'000780 H'000781 H'000782 EB2 Erase unit 1 kbyte H'000800 H'000801 H'000802 EB3 Erase unit 1 kbyte EB4 Erase unit 28 kbytes EB5 Erase unit 16 kbytes EB6 Erase unit 8 kbytes EB7 Erase unit 8 kbytes EB8 Erase unit 32 kbytes EB9 Erase unit 32 kbytes H'000B80 H'000B81 H'000B82 H'000C00 H'000C01 H'000C02 H'000F80 H'000F8
Section 20 Flash Memory (F-ZTAT Version) 20.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 20.2. Table 20.
Section 20 Flash Memory (F-ZTAT Version) 20.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 20.8, Flash Memory Programming/Erasing. Bit Bit Name Initial Value R/W Description 7 FWE — Flash Write Enable Bit R Reflects the input level at the FWE pin.
Section 20 Flash Memory (F-ZTAT Version) Bit Bit Name Initial Value R/W Description 2 PV1 0 Program-Verify R/W When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. [Setting condition] When FWE = 1 and SWE1 = 1 1 E1 0 R/W Erase When this bit is set to 1, and while the SWE1 and ESU1 bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled.
Section 20 Flash Memory (F-ZTAT Version) • 384-kbyte or 256-kbyte Flash Memory Bit Bit Name Initial Value R/W Description 7 EB7 0 R/W When this bit is set to 1, 4 kbytes of EB7 (H'007000 to H'007FFF) will be erased. 6 EB6 0 R/W When this bit is set to 1, 4 kbytes of EB6 (H'006000 to H'006FFF) will be erased. 5 EB5 0 R/W When this bit is set to 1, 4 kbytes of EB5 (H'005000 to H'005FFF) will be erased.
Section 20 Flash Memory (F-ZTAT Version) 20.5.4 Erase Block Register 2 (EBR2) EBR2 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE1 bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. • 384-kbyte Flash Memory Bit Bit Name Initial Value R/W Description 7, 6 — All 0 Reserved R/W These bits are always read as 0. The write value should always be 0.
Section 20 Flash Memory (F-ZTAT Version) • 128-kbyte Flash Memory Bit Bit Name Initial Value R/W Description 7 to 2 — All 0 R/W Reserved 1 EB9 0 R/W When this bit is set to 1, 32 kbytes of EB9 (H'018000 to H'01FFFF) will be erased. 0 EB8 0 R/W When this bit is set to 1, 32 kbytes of EB8 (H'010000 to H'017FFF) will be erased. Initial values should not be changed. 20.5.
Section 20 Flash Memory (F-ZTAT Version) Bit Bit Name Initial Value R/W Description 2 RAM2 0 R/W Flash Memory Area Selection 1 RAM1 0 R/W 0 RAM0 0 R/W When the RAMS bit is set to 1, one of the following flash memory areas is selected to overlap the RAM area. The areas correspond with 4-kbyte erase blocks for the 384kbyte or 256-kbyte flash memory, 1-kbyte erase block for the 128-kbyte flash memory.
Section 20 Flash Memory (F-ZTAT Version) 20.5.6 Flash Memory Power Control Register (FLPWCR) FLPWCR enables/disables transition to power-down modes for the flash memory when this LSI enters sub-active mode. Bit Bit Name Initial Value R/W Description 7 PDWND 0 Power Down Disable R/W Enables/disables transition to power-down modes for the flash memory when this LSI enters sub-active mode. 0: Transition to power-down modes for the flash memory enabled.
Section 20 Flash Memory (F-ZTAT Version) Bit Bit Name Initial Value R/W Description 3 FLSHE 0 Flash Memory Control Register Enable R/W Controls for the CPU accessing to the control registers (FLMCR1, FLMCR2, EBR1, EBR2) of the flash memory. When this bit is set to 1, the flash memory control registers can be read/written to. When this bit is cleared to 0, the flash memory control registers are not selected. At this time, the contents of the flash memory control registers are retained.
Section 20 Flash Memory (F-ZTAT Version) In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 2. SCI should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3.
Section 20 Flash Memory (F-ZTAT Version) Table 20.4 Boot Mode Operation Item Boot mode start Host Operation Processing Contents Communications Contents LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Bit rate adjustment Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 ...... H'00 · Measures low-level period of receive data H'00.
Section 20 Flash Memory (F-ZTAT Version) 20.6.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must prepare onboard means for controlling FWE, on-board means of supplying programming data, and branching conditions.
Section 20 Flash Memory (F-ZTAT Version) 1. Set RAMER to overlap part of RAM onto the area for which real-time programming is required. 2. Emulation is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space.
Section 20 Flash Memory (F-ZTAT Version) 4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). In this state, setting the P1 or E1 bit in FLMCR1 to 1 does not cause a transition to program mode or erase mode. 5. A RAM area cannot be erased by execution of software in accordance with the erase algorithm. 6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM.
Section 20 Flash Memory (F-ZTAT Version) mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 20.8.1, Program/Program-Verify and section 20.8.2, Erase/Erase-Verify, respectively. 20.8.
Section 20 Flash Memory (F-ZTAT Version) Write pulse application subroutine Start of programming Sub-Routine Write Pulse START Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 20 Flash Memory (F-ZTAT Version) 20.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 20.12 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E1 bit is set to 1 is the flash memory erase time.
Section 20 Flash Memory (F-ZTAT Version) Erase start *1 Erasing should be done to a block SWE1 bit in FLMCR1 ← 1 tsswe: Wait 1 μs n=1 *3 Set EBR1 (2) Enable WDT ESU1 bit in FLMCR1 ← 1 tsswe: Wait 100 μs E1 bit in FLMCR1 ← 1 start erasing tse: Wait 10 ms *5 E1 bit in FLMCR1 ← 0 stop erasing tce: Wait 10 μs ESU1 bit in FLMCR1 ← 0 tcesu: Wait 10 μs Disable WDT EV1 bit in FLMCR ← 1 tsev: Wait 20 μs Set block start address as verify address H'FF dummy write to verify address tsevr: Wait 2 μs Verify
Section 20 Flash Memory (F-ZTAT Version) 20.9 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 20.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode.
Section 20 Flash Memory (F-ZTAT Version) The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a reset or in hardware standby. 20.
Section 20 Flash Memory (F-ZTAT Version) This LSI Pin No. BP-112*2 TBP-112A*5 Pin Name 16 F1 18 G1 16 19 17 Socket Adapter (Conversion to 40-Pin Arrangement) HN27C4096HG (40-Pin) Pin No.
Section 20 Flash Memory (F-ZTAT Version) 20.12 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: • Normal operating mode The flash memory can be read and written to at high speed. • Power-down state The flash memory can be read when part of the power circuit is halted and the LSI operates by subclocks. • Standby mode All flash memory circuits are halted. Table 20.
Section 20 Flash Memory (F-ZTAT Version) Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. Powering On and Off (See Figures 20.14 to 20.16): Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state.
Section 20 Flash Memory (F-ZTAT Version) Do Not Set or Clear the SWE1 Bit during Execution of a Program in Flash Memory: Wait for at least 100 µs after clearing the SWE1 bit before executing a program or reading data in flash memory. When the SWE1 bit is set, data in flash memory can be rewritten. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE1 bit during programming, erasing, or verifying.
Section 20 Flash Memory (F-ZTAT Version) Wait time: tsswe Programming/ erasing possible Wait time: 100 μs φ min 0 μs tOSC1 VCC tMDS*3 FWE min 0 μs MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1bit Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Section 20 Flash Memory (F-ZTAT Version) Programming/ erasing Wait time: tsswe possible Wait time: 100 μs φ min 0 μs tOSC1 VCC FWE MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
*4 *4 Programming/ erasing possible Wait time: tsswe Wait time: tsswe Programming/ erasing possible Wait time: tsswe Programming/ erasing possible Programming/ erasing possible Wait time: tsswe Section 20 Flash Memory (F-ZTAT Version) *4 *4 φ tOSC1 VCC min 0ms FWE *2 tMDS tMDS MD2 to MD0 tMDS tRESW RES SWE1 cleared SWE1 set SWE1 bit Mode change*1 Boot mode Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohibited (tsswe: W
Section 20 Flash Memory (F-ZTAT Version) 20.14 Note on Switching from F-ZTAT Version to Masked ROM Version The masked ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 20.7 lists the registers that are present in the F-ZTAT version but not in the masked ROM version. If a register listed in table 20.7 is read in the masked ROM version, an undefined value will be returned.
Section 20 Flash Memory (F-ZTAT Version) Rev. 6.00 Mar.
Section 21 Masked ROM Section 21 Masked ROM This LSI incorporates a masked ROM which has the following features. 21.
Section 21 Masked ROM Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Figure 21.1 H'000000 H'000001 H'000002 H'000003 H'05FFFE H'05FFFF Block Diagram of On-Chip Masked ROM (384 kbytes) Rev. 6.00 Mar.
Section 22 PROM Section 22 PROM The PROM version can be set to PROM mode and programmed with a PROM programmer. 22.1 PROM Mode Setting The PROM version (HD6472237) suspends its microcomputer functions when placed in PROM mode, enabling the on-chip PROM to be programmed. This programming can be done with a PROM programmer set up in the same way as for the HN27C101 (VPP = 12.5 V) EPROM. Use of a socket adapter to convert from 100 pins to 32 pins enables programming with a commercial PROM programmer.
Section 22 PROM HD6472237 (FP-100B, TFP-100B, TFP-100G) EPROM socket HN27C101 (DIP-32) Pin No. Pin No.
Section 22 PROM HD6472237 (FP-100A) EPROM socket HN27C101 (DIP-32) Pin No. Pin No.
Section 22 PROM Table 22.2 Socket Adapters Socket Adapter Product Name Package Minato Electronics Data IO Japan H8S/2237 100-pin TQFP (TFP-100B) ME2237ESNS1H H7223BT100D3201 100-pin TQFP (TFP-100G) ME2237ESMS1H H7223GT100D3201 100-pin QFP (FP-100A) ME2237ESFS1H H7223AQ100D3201 100-pin QFP (FP-100B) ME2237ESHS1H H7223BQ100D3201 Address in MCU mode Address in PROM mode H'000000 H'00000 On-chip PROM H'01FFFF H'1FFFF Figure 22.3 Memory Map in PROM Mode Rev. 6.00 Mar.
Section 22 PROM 22.3 Programming Table 22.3 shows how to select the program, verify, and other modes in PROM mode. Table 22.
Section 22 PROM Start Set program/verification mode VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V Address = 0 n=0 n+1→n Yes No Program width tPW = 0.2 ms ± 5% n < 25 Address + 1 → address No Verification? Yes Program width tOPW = 0.2n ms No Last address? Yes Set read mode VCC = 5.0 V ± 0.25 V, VPP = VCC Fail No go All address read? Go End Figure 22.4 High-Speed Programming Flowchart Rev. 6.00 Mar.
Section 22 PROM Table 22.4 DC Characteristics in PROM Mode (Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Symbol Min Typ Max Test Unit Conditions — VCC + 0.3 V V Input high voltage EO7 to EO0, EA16 to EA0, OE, CE, PGM VIH 2.4 Input low voltage EO7 to EO0, EA16 to EA0, OE, CE, PGM VIL –0.3 — 0.8 Output high voltage EO7 to EO0 VOH 2.4 — — V IOH = –200 µA Output low voltage EO7 to EO0 VOL — — 0.45 V IOL = 1.
Section 22 PROM Table 22.5 AC Characteristics in PROM Mode (Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C) Item Symbol Min Typ Max Unit Test Conditions Address setup time tAS 2 — — µs Figure 22.5* OE setup time tOES 2 — — µs Data setup time tDS 2 — — µs Address hold time tAH 0 — — µs Data hold time 2 — — µs Data output disable time tDH 2 t * — — 130 ns VPP setup time tVPS 2 — — µs Programming pulse width tPW 0.19 0.20 0.21 ms 0.
Section 22 PROM Program Verification Address tAS tAH Input data Data tDS VPP VCC Output data tDH tDF VPP VCC tVPS VCC +1 VCC tVCS CE tCES PGM tPW OE tOES tOE tOPW* Note: * tOPW is defined by the value shown in the flowchart. Figure 22.5 PROM Programming/Verification Timing 22.3.2 Programming Precautions • Program using the specified voltages and timing. The programming voltage (VPP) in PROM mode is 12.5 V. Applied voltages in excess of the specified values can permanently destroy the MCU.
Section 22 PROM • The size of the PROM is 128 kbytes. Always set addresses within the range H'00000 to H'1FFFF. During programming, write H'FF to unused addresses to avoid verification errors. 22.3.3 Reliability of Programmed Data An effective way to assure the data retention characteristics of the programmed chips is to bake them at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 22.
Section 23 Clock Pulse Generator Section 23 Clock Pulse Generator This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, duty adjustment circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, and wave formation circuit. A block diagram of the clock pulse generator is shown in figure 23.1.
Section 23 Clock Pulse Generator 23.1 Register Descriptions The on-chip clock pulse generator has the following registers. • System clock control register (SCKCR) • Low-power control register (LPWRCR) 23.1.1 System Clock Control Register (SCKCR) SCKCR performs medium-speed mode control. Bit Bit Name Initial Value R/W Description 7 PSTOP 0 R/W φ Clock Output Prohibited Controls φ output.
Section 23 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 2 SCK2 0 R/W System Clock Select 2 to 0 1 SCK1 0 R/W These bits select the bus master clock. 0 SCK0 0 R/W 000: High-speed mode 001: Medium-speed clock φ/2 010: Medium-speed clock φ/4 011: Medium-speed clock φ/8 100: Medium-speed clock φ/16 101: Medium-speed clock φ/32 11×: Setting prohibited Legend: ×: Don’t care Rev. 6.00 Mar.
Section 23 Clock Pulse Generator 23.1.2 Low-Power Control Register (LPWRCR) LPWRCR performs down-mode control, selects sampling frequency for eliminating noise, performs subclock generation control, and specifies multiplication factor. Bit Bit Name Initial Value R/W Description 7 DTON 0 R/W Direct Transfer ON Flag 0: When the SLEEP instruction is executed in highspeed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*.
Section 23 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 5 NESEL 0 R/W Noise Elimination Sampling Frequency Select This bit selects the sampling frequency of the subclock (φSUB) generated by the subclock oscillator is sampled by the clock (φ) generated by the system clock oscillator Set 0 when φ is 5 MHz or higher. Set 1 when φ is 2.1 MHz or lower. Any value can be set when φ is 2.1 to 5 MHz.
Section 23 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 1 STC1 0 R/W Multiplication factor setting 0 STC0 0 R/W Specifies multiplication factor of the PLL circuit built in the evaluation chip. The specified multiplication factor becomes valid software standby mode, watch mode, or subactive mode is entered. These bits should be set to 11 in this LSI. Since the value becomes STC1 = STC0 = 0 after a reset, set STC1 = STC0 = 1.
Section 23 Clock Pulse Generator Table 23.1 Damping Resistance Value Frequency (MHz) 2* Rd (Ω) 1k 1 4* 1 500 6* 8* 1 300 1 200 10 12 16* 100 0 0 2 20* 2 0 Notes: 1. The H8S/2258 Group is out of operation. 2. Supported only by the H8S/2239 Group. Figure 23.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 23.2. CL XTAL L Rs EXTAL AT-cut parallel-resonance type C0 Figure 23.
Section 23 Clock Pulse Generator External clock input EXTAL Open XTAL (a) XTAL pin left open External clock input EXTAL XTAL (b) Complementary clock input at XTAL pin Figure 23.4 External Clock Input (Examples) Table 23.3 shows the input conditions for the external clock. Table 23.4 shows the input conditions for the external clock when duty adjustment circuit is not used. Table 23.3 External Clock Input Conditions (1) (H8S/2258 Group) VCC = 4.0 V to 5.
Section 23 Clock Pulse Generator Table 23.3 External Clock Input Conditions (2) (H8S/2238B, H8S/2236B) F-ZTAT Masked ROM VCC = 3.0 V to 5.5 V VCC = 2.7 V to 5.5 V Item Symbol Min Max Min Max Unit Test Conditions Figure 23.5 External clock input tEXL low pulse width 30 — 30 — ns External clock input tEXH high pulse width 30 — 30 — ns External clock rise time tEXr — 7 — 7 ns External clock fall time tEXf — 7 — 7 ns Clock low pulse width tCL 0.4 0.6 0.4 0.
Section 23 Clock Pulse Generator Table 23.3 External Clock Input Conditions (4) (H8S/2237 Group, H8S/2227 Group) F-ZTAT and Masked ROM Masked ROM ZTAT VCC = 2.7 V to 3.6 V VCC = 2.2 V to 3.6 V VCC = 2.7 V to 3.
Section 23 Clock Pulse Generator Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (1) (H8S/2258 Group) VCC = 4.0 V to 5.5 V Item Symbol Min Max Unit Test Conditions External clock input low pulse width tEXL 37 — ns Figure 23.
Section 23 Clock Pulse Generator Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (3) (H8S/2238R, H8S/2236R) F-ZTAT and Masked ROM F-ZTAT VCC = 2.7 V to 3.6 V VCC = 2.2 V to 3.6 V Item Symbol Min Max Min Max Unit Test Conditions Figure 23.
Section 23 Clock Pulse Generator Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (5) (H8S/2239 Group) F-ZTAT and Masked ROM VCC = 3.0 V to 3.6 V Item Symbol Min Masked ROM VCC = 2.7 V to 3.6 V Max Min Max VCC = 2.2 V to 3.6 V Min Max Unit Test Conditions Figure 23.5 External clock input tEXL low pulse width 25 — 31.25 — 80 — ns External clock input tEXH high pulse width 25 — 31.25 — 80 — ns External clock rise time tEXr — 5 — 6.
Section 23 Clock Pulse Generator This LSI External clock switch request Control circuit External interrupt signal Port output External interrupt External clock 1 External clock 2 Selector External clock switch signal EXTAL Figure 23.
Section 23 Clock Pulse Generator 23.3 Duty Adjustment Circuit The duty adjustment circuit is valid when oscillation frequency is more than 5 MHz. The duty adjustment circuit adjusts clock output fr/m the system clock oscillator to generate the system clock (φ). 23.4 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32. 23.
Section 23 Clock Pulse Generator 23.7 Subclock Oscillator 23.7.1 Connecting 32.768-kHz Crystal Resonator To supply a clock to the subclock divider, connect a 32.768-kHz crystal resonator, as shown in figure 23.8. Figure 23.9 shows the equivalence circuit for a 32.768-kHz oscillator. C1 OSC1 C2 OSC2 C1 = C2 = 15 pF (typ) Note: CL1 and CL2 are reference values including the floating capacitance of the board. Figure 23.8 Connection Example of 32.
Section 23 Clock Pulse Generator 23.7.2 Handling Pins when Subclock Not Required If no subclock is required, connect the OSC1 pin to Vss and leave OSC2 open, as shown in figure 23.10. The SUBSTP bit in LPWRCR must be set to 1. If the SUBSTP bit is not set to 1, transitions to the power-down modes may not complete normally. On the H8S/2237 and H8S/2227 Group, the OSC1 pin should be connected to VCC. OSC1 Open OSC2 Figure 23.10 Pin Handling when Subclock Not Required 23.
Section 23 Clock Pulse Generator 23.9.2 Note on Board Design When designing the board, place the crystal resonator and its load capacitors as close as possible to the EXTAL, XTAL, OSC1, and OSC2 pins. Make wires as short as possible. Other signal lines should be routed away from the oscillator circuit, as shown in figure 23.11. This is to prevent induction from interfering with correct oscillation. Signal A Signal B Avoid C1 This LSI EXTAL, OSC1 XTAL, OSC2 C2 Figure 23.
Section 24 Power-Down Modes Section 24 Power-Down Modes In addition to the normal program execution state, this LSI has nine power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on. This LSI operating modes are as follows: 1. High-speed mode 2. Medium-speed mode 3. Subactive mode 4. Sleep mode 5. Subsleep mode 6. Watch mode 7. Module stop mode 8.
Section 24 Power-Down Modes Table 24.
Section 24 Power-Down Modes 4. Supported only by the H8S/2258 Group. 5. The analog output value does not satisfy the specified D/A absolute accuracy when D/A is halted (retained). However, the H8S/2258 Group, H8S/2238B, and H8S/2236B satisfy the specified D/A absolute accuracy.
Section 24 Power-Down Modes Table 24.
Section 24 Power-Down Modes 24.1 Register Description The following registers relates to the power-down modes. For details on system clock control register (SCKCR), refer to section 23.1.1, System Clock Control Register (SCKCR). For details on low power control register (LPWRCR), refer to section 23.1.2, Low Power Control Register (LPWRCR). For details on timer control status register (TCSR_1), refer to section 13.3.2, Timer Control/Status Register (TCSR).
Section 24 Power-Down Modes Bit Bit Name Initial Value R/W Description 6 STS2 0 R/W Standby Timer Select 2 to 0 5 STS1 0 R/W 4 STS0 0 R/W These bits select the MCU wait time for clock settling to cancel software standby mode, watch mode, or subactive mode. With a crystal resonator (tables 24.3, 27.5, 27.17, 27.30, 27.42, 27.53), select a wait time of tOSC2 ms (oscillation settling time) or more, depending on the operating frequency.
Section 24 Power-Down Modes 24.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC) MSTPCR performs module stop mode control. When bits in MSTPCR registers are set to 1, module stop mode is set. When cleared to 0, module stop mode is cleared.
Section 24 Power-Down Modes • MSTPCRC Bit Bit Name Initial Value R/W Target Module 7 MSTPC7 1 R/W Serial communication interface 3 (SCI_3) 6 1 MSTPC6* 1 R/W 5 MSTPC5 1 R/W 4 D/A converter* 4 MSTPC4 1 R/W PC break controller (PBC) 3 MSTPC3 1 R/W IEBus controller (IEB)* 2 1 R/W 1 MSTPC2* 1 MSTPC1* 1 R/W 0 1 MSTPC0* 1 R/W 1 5 Notes: 1. Bits MSTPA3, MSTPA2, MSTPB5, MSTPB2 to MSTPB0, MSTPC6, MSTPC2 to MSTPC0 are readable/writable. The initial value of them is 1.
Section 24 Power-Down Modes When the SLEEP instruction is executed with the SSBY bit = 1, the LSON bit in LPWRCR = 0, and the PSS bit in TCSR_1 (WDT_1) = 0, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES or MRES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer.
Section 24 Power-Down Modes 24.3.2 Exiting Sleep Mode Sleep mode is exited by any interrupt, or signals at the RES pin, MRES pin, or STBY pin. • Exiting Sleep Mode by Interrupts When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. • Exiting Sleep Mode by RES Pin or MRES Pin Setting the RES pin or MRES pin level low selects the reset state.
Section 24 Power-Down Modes than interrupts IRQ7 to IRQ0 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. • Clearing with the RES Pin or MRES Pin When the RES pin or MRES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire this LSI chip. Note that the RES pin or MRES pin must be held low until clock oscillation settles.
Section 24 Power-Down Modes 24.4.4 Software Standby Mode Application Example Figure 24.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin.
Section 24 Power-Down Modes 24.5 Hardware Standby Mode 24.5.1 Transition to Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state.
Section 24 Power-Down Modes Oscillator RES STBY Oscillation settling time tosc1 Reset exception handling Figure 24.4 Hardware Standby Mode Timing 24.6 Module Stop Mode Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently.
Section 24 Power-Down Modes 24.7 Watch Mode 24.7.1 Transition to Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in highspeed mode or subactive mode with SSBY in SBYCR = 1, DTON in LPWRCR = 0, and PSS in TCSR_1 (WDT_1) = 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1 and system clock oscillator are also stopped.
Section 24 Power-Down Modes 24.8 Subsleep Mode 24.8.1 Transition to Subsleep Mode When the SLEEP instruction is executed with the SSBY bit in SBYCR = 0, the LSON bit in LPWRCR = 1, and the PSS bit in TCSR_1 (WDT_1) = 1 in subactive mode, CPU operation shifts to subsleep mode. In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0 to TMR3, WDT_0, and WDT_1 and system clock oscillator are also stopped.
Section 24 Power-Down Modes 24.9 Subactive Mode 24.9.1 Transition to Subactive Mode When the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, CPU operation shifts to subactive mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a transition is made to subactive mode. And if an interrupt occurs in subsleep mode, a transition is made to subactive mode.
Section 24 Power-Down Modes 24.10 Direct Transitions There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution when shifting between high-speed and subactive modes. Direct transitions are enabled by setting the LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct transition interrupt exception processing starts. 24.10.
Section 24 Power-Down Modes 24.12 Usage Notes 24.12.1 I/O Port Status In software standby mode and watch mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 24.12.2 Current Dissipation during Oscillation Settling Wait Period Current dissipation increases during the oscillation settling wait period. 24.12.
Section 24 Power-Down Modes 24.12.5 Writing to MSTPCR MSTPCR should only be written to by the CPU. 24.12.6 Entering Subactive/Watch Mode and DMAC* and DTC Module Stop To enter subactive or watch mode, set DMAC* and DTC to module stop (write 1 to the MSTPA6 bit and MSTPA7 bit) and reading the MSTPA6 bit and MSTPA7 bit as 1 before transiting mode. After transiting from subactive mode to active mode, clear module stop.
Section 25 Power Supply Circuit Section 25 Power Supply Circuit 25.1 Overview The H8S/2258 Group, H8S/2238B, and H8S/2236B incorporates an internal power supply stepdown circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.
Section 25 Power Supply Circuit VCC Step-down circuit Internal logic H8S/2258 Group: VCC = 4.0 V to 5.5 V H8S/2238B, H8S/2236B: VCC = 2.7 V to 5.5 V (In the F-ZTAT version, VCC = 3.0 V to 5.5 V) CVCC Stabilization capacitance (approx. 0.1 µF) Internal power supply VSS Figure 25.1 Power Supply Connection for H8S/2258 Group, H8S/2238B, and H8S/2236B (On-Chip Internal Power Supply Step-Down Circuit) 25.
Section 25 Power Supply Circuit 25.4 Note on Bypass Capacitor A laminated ceramic capacitor of 0.01 μF to 0.1 μF should be inserted as a bypass capacitor in each pair of VSS and VCC. The bypass capacitor should be placed as close as possible to the power supply pin of this LSI. The capacitance value and frequency characteristics should be used according to the operating frequency of this LSI. Rev. 6.00 Mar.
Section 25 Power Supply Circuit Rev. 6.00 Mar.
Section 26 List of Registers Section 26 List of Registers This section gives information on the on-chip I/O registers and is configured as described below. 1. Register Addresses (In Address Order) ⎯ Descriptions by functional module, in ascending order of addresses ⎯ Descriptions by functional module ⎯ The number of access states are given 2.
Section 26 List of Registers Register Name Abbreviation Bit No.
Section 26 List of Registers Register Name Abbreviation Bit No.
Section 26 List of Registers Register Name Abbreviation Bit No.
Section 26 List of Registers Register Name Abbreviation Bit No.
Section 26 List of Registers Register Name Abbreviation Bit No.
Section 26 List of Registers Register Name Abbreviation Bit No.
Section 26 List of Registers Register Name Abbreviation Bit No.
Section 26 List of Registers Register Name Abbreviation Bit No.
Section 26 List of Registers Abbreviation Bit No.
Section 26 List of Registers Register Name Abbreviation Bit No.
Section 26 List of Registers 26.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit register is shown as 2 lines.
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IELA2 ⎯ ⎯ ⎯ ⎯ ILA11 ILA10 ILA9 ILA8 IEB IEFLG CMX MRQ SRQ SRE LCK ⎯ RSS GG IETSR TxRDY ⎯ ⎯ ⎯ IRA TxS TxF TxE IEIET TxRDYE ⎯ ⎯ ⎯ IRAE TxSE TxFE TxEE IETEF ⎯ ⎯ ⎯ AL UE TTME RO ACK IERSR RxRDY ⎯ ⎯ ⎯ ⎯ RxS RxF RxE IEIER RxRDYE ⎯ ⎯ ⎯ ⎯ RxSE RxFE RxEE IEREF ⎯ ⎯ ⎯ ⎯ OVE RTME DLE PE DADR_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SBYCR SSBY STS2 STS1 STS0 OPE ⎯ ⎯ ⎯ SYSTEM SYSCR ⎯ ⎯ INTM1 INTM0 NMIEG MRESE ⎯ RAME SCKCR PSTOP ⎯ ⎯ ⎯ ⎯ SCK2 SCK1 SCK0 MDCR ⎯ ⎯ ⎯ ⎯ ⎯ MDS2 MDS1 MDS0 MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR PORT P3DDR ⎯ P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P7DDR P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR PADDR ⎯ ⎯ ⎯ ⎯ PA3DDR PA2DDR PA1DDR PA0DDR PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DD
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TGRD_3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TPU_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCR_4 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_4 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 TIOR_4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_4 TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB TGIEA TSR_4 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA TCNT_4 Bit 15 Bit
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IPRF ⎯ IPR6 IPR5 IPR4 ⎯ IPR2 IPR1 IPR0 INT IPRG ⎯ IPR6 IPR5 IPR4 ⎯ IPR2 IPR1 IPR0 IPRH ⎯ IPR6 IPR5 IPR4 ⎯ IPR2 IPR1 IPR0 IPRI ⎯ IPR6 IPR5 IPR4 ⎯ IPR2 IPR1 IPR0 IPRJ ⎯ IPR6 IPR5 IPR4 ⎯ IPR2 IPR1 IPR0 IPRK ⎯ IPR6 IPR5 IPR4 ⎯ IPR2 IPR1 IPR0 IPRL ⎯ IPR6 IPR5 IPR4 ⎯ IPR2 IPR1 IPR0 IPRO ⎯ IPR6 IPR5 IPR4 ⎯ IPR2 IPR1 IPR0 ABWCR ABW7 AB
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MAR_1A ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DMAC Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 IOAR_1A ETCR_1A MAR_1B Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TSR_0 ⎯ ⎯ ⎯ TCFV TGFD TGFC TGFB TGFA TPU_0 TCNT_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TGRB_2 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TPU_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DMAWER ⎯ ⎯ ⎯ ⎯ WE1B WE1A WE0B WE0A DMATCR ⎯ ⎯ TEE1 TEE0 ⎯ ⎯ ⎯ ⎯ DMACR_0A*2 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 DMACR_0A* DTSZ SAID SAIDE BLKDIR BLKE ⎯ ⎯ ⎯ DMACR_0B* DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 DMACR_0B*3 ⎯ DAID
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ICCR_0 ICE IEIC MST TRS ACKE BBSY IRIC SCP IIC_0 BRR_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCI_0 ICSR_0 ESTP STOP IRTR AASX AL AAS ADZ ACKB IIC_0 SCR_0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE RDRF ORER FER PER TEND MPB MPBT (TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT)
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TDR_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCI_2 SSR_2*1 TDRE RDRF ORER FER PER TEND MPB MPBT (TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT) RDR_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCMR_2 ⎯ ⎯ ⎯ ⎯ SDIR SINV ⎯ SMIF ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRAL AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADDRBH AD9 AD8 AD7 AD6 AD5
Section 26 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORT PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PORTG ⎯ ⎯ ⎯ PG4 PG3 PG2 PG1 PG0 Notes: 1. Some bit names differ depending on whether used in normal mode and Smart Card interface mode. The name in ( ) indicates the name in Smart Card interface mode. 2. Short address mode 3. Full address mode Rev. 6.00 Mar.
Section 26 List of Registers 26.
Section 26 List of Registers Register Name Reset DADR_0 Manual Reset Highspeed Mediumspeed Sleep Module Stop Watch Subactive Subsleep Software Hardware Standby Standby Module Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DADR_1 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DACR Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCRX Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DDCSWR Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initia
Section 26 List of Registers Register Name Reset BARA Manual Reset Highspeed Mediumspeed Sleep Module Stop Watch Subactive Subsleep Software Hardware Standby Standby Module Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized BARB Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized BCRA Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized BCRB Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ISCRH Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized
Section 26 List of Registers Register Name Reset Manual Reset Highspeed Mediumspeed Sleep Module Stop Watch Subactive Subsleep Software Hardware Standby Standby Module PAODR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PORT TCR_3 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_3 TMDR_3 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIORH_3 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIORL_3 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Section 26 List of Registers Register Name Reset IPRA Manual Reset Highspeed Mediumspeed Sleep Module Stop Watch Subactive Subsleep Software Hardware Standby Standby Module Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRB Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRC Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRD Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRE Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized
Section 26 List of Registers Register Name Reset P1DR Manual Reset Highspeed Mediumspeed Sleep Module Stop Watch Subactive Subsleep Software Hardware Standby Standby Module Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized P3DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized P7DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PADR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PBDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PCDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Section 26 List of Registers Register Name Reset TCR_2 Manual Reset Highspeed Mediumspeed Sleep Module Stop Watch Subactive Subsleep Software Hardware Standby Standby Module Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TMDR_2 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIOR_2 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIER_2 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TSR_2 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Init
Section 26 List of Registers Register Name Reset BRR_0 ICSR_0 Manual Reset Highspeed Mediumspeed Sleep Module Stop Watch Subactive Subsleep Software Hardware Standby Standby Module Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCI_0 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IIC_0 SCR_0 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCI_0 TDR_0 Initialized Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized Initialized Initializ
Section 26 List of Registers Register Name Reset ADDRAH ADDRAL Mediumspeed Sleep Module Stop Initialized Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized Initialized Initialized ADDRBH Initialized Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized Initialized Initialized ADDRBL Initialized Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized
Section 27 Electrical Characteristics Section 27 Electrical Characteristics 27.1 Power Supply Voltage and Operating Frequency Range Figures 27.1, 27.2, 27.3, 27.4, and 27.5 show power supply voltage and operating frequency ranges (shaded areas) of the H8S/2258 Group, H8S/2239 Group, H8S/2238B, H8S/2236B, H8S/2238R, H8S/2236R, and H8S/2237 Group and H8S/2227 Group respectively. (1) Power supply voltage and oscillation frequency range f (MHz) 13.5 f (kHz) 32.768 10.0 0 4.0 5.
Section 27 Electrical Characteristics (1) Power supply voltage/analog power supply voltage and oscilllation frequency range (F-ZTAT version) f (MHz) 20.0 16.0 System clock f (kHz) 32.768 Subclock 6.25 2.0 0 2.2 2.7 3.0 3.6 5.5 Vcc (V) AVcc · Active (high/medium speed) mode · Sleep mode 0 2.2 2.7 3.6 · All operating mode 5.5 Vcc (V) (2) Power supply voltage/analog power supply voltage and oscilllation frequency range (Masked ROM version) f (MHz) 20.0 16.0 f (kHz) 32.768 System clock Subclock 6.
Section 27 Electrical Characteristics (1) Power supply voltage and oscillation frequency range (F-ZTAT version) f (MHz) 13.5 System clock f (kHz) 32.768 Subclock 6.25 2.0 0 5.5 Vcc (V) 2.2 2.7 3.0 3.6 · Active (high-speed/medium-speed) mode · Sleep mode 0 2.7 3.0 3.6 2.2 · All operating modes 5.5 Vcc (V) (2) Power supply voltage and oscillation frequency range (Masked ROM version) f (MHz) 13.5 System clock f (kHz) 32.768 Subclock 6.25 2.0 0 2.2 2.7 3.6 5.
Section 27 Electrical Characteristics (1) Power supply voltage/analog power supply voltage and oscilllation frequency range (F-ZTAT-version wide-range specifications) f (MHz) f (kHz) 32.768 System clock 13.5 Subclock 6.25 2.0 0 2.2 2.7 3.6 · Active (high/medium speed) mode · Sleep mode 5.5 Vcc (V) AVcc 0 2.2 2.7 3.6 5.
Section 27 Electrical Characteristics (1) Power supply voltage oscilllation frequency range (ZTAT version) f (MHz) f (kHz) System clock 13.5 32.768 10.0 Subclock 6.25 2.0 0 2.2 2.7 3.0 3.6 Vcc (V) 2.2 2.7 3.0 3.6 Vcc (V) · Active (high/medium speed) mode AVcc · All operating mode · Sleep mode (2) Power supply voltage/analog power supply voltage and oscilllation frequency range (F-ZTAT version) f (MHz) f (kHz) System clock 13.5 32.768 Subclock 6.25 2.0 0 2.2 2.7 3.0 3.6 Vcc (V) 0 2.2 2.7 3.
Section 27 Electrical Characteristics 27.2 Electrical Characteristics of H8S/2258 Group 27.2.1 Absolute Maximum Ratings Table 27.1 lists the absolute maximum ratings. Table 27.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +7.0 V CVCC −0.3 to +4.3 V Input voltage (except ports 4 and 9) Vin −0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin −0.3 to AVCC +0.3 V Reference power supply voltage Vref −0.3 to AVCC +0.
Section 27 Electrical Characteristics 27.2.2 DC Characteristics Table 27.2 lists the DC characteristics. Table 27.3 lists the permissible output currents. Table 27.4 lists the bus driving characteristics. Table 27.2 DC Characteristics (1) Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.
Section 27 Electrical Characteristics Item Input leakage current Three states leakage current (off) Test Conditions Symbol Min Typ Max Unit | Iin | ⎯ ⎯ 1.0 µA STBY, NMI, MD2 to MD0, FWE ⎯ ⎯ 1.0 µA Ports 4 and 9 ⎯ ⎯ 1.0 µA Vin = 0.5 to AVCC – 0.5 V | ITSI | ⎯ ⎯ 1.0 µA Vin = 0.5 to VCC – 0.5 V –IP 10 ⎯ 300 µA Vin = 0V RES Ports 1, 3, 7, and A to G Input pull-up Ports A to E MOS current Vin = 0.5 to VCC – 0.5 V Notes: 1.
Section 27 Electrical Characteristics Table 27.2 DC Characteristics (2) Conditions (F-ZTAT version):VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Item Input capacitance Symbol Min Test Conditions Typ Max Unit ⎯ ⎯ 30 pF NMI ⎯ ⎯ 30 pF P32 to P35 ⎯ ⎯ 20 pF All input pins other than above ones ⎯ ⎯ 15 pF ⎯ 28 40 mA VCC = 5.0 V VCC = 5.5 V f = 13.
Section 27 Electrical Characteristics Item Typ Max Unit 1.5 10 µA ⎯ ⎯ 50 ⎯ 0.4 1.5 mA Waiting for A/D or D/A conversion ⎯ 0.01 5.0 µA During A/D or AlCC D/A conversion ⎯ 2.1 3.5 mA Waiting for A/D or D/A conversion ⎯ 0.01 5.0 µA 2.0 ⎯ ⎯ V Current Standby 2 3 consumption* mode* Symbol Min 4 ⎯ ICC* Analog power During A/D or AlCC supply current D/A conversion Reference power supply current RAM standby voltage VRAM Test Conditions Ta ≤ 50°C, When 32.
Section 27 Electrical Characteristics Table 27.2 DC Characteristics (3) Conditions (masked ROM version): VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range 1 specifications)* Item Input capacitance Symbol Min Test Conditions Typ Max Unit ⎯ ⎯ 30 pF NMI ⎯ ⎯ 30 pF P32 to P35 ⎯ ⎯ 20 pF All input pins other than above ones ⎯ ⎯ 15 pF ⎯ 25 40 mA VCC = 5.0 V VCC = 5.
Section 27 Electrical Characteristics Item Symbol Min Current Standby 2 3 consumption* mode* 4 ICC* Analog power During A/D or AlCC supply current D/A conversion Waiting for A/D or D/A conversion Reference During A/D or AlCC power supply D/A current conversion Waiting for A/D or D/A conversion RAM standby voltage VRAM Typ Max Unit ⎯ 1.0 10 µA ⎯ ⎯ 50 ⎯ 0.4 1.5 mA ⎯ 0.01 5.0 µA ⎯ 2.1 3.5 mA ⎯ 0.01 5.0 µA 2.0 ⎯ ⎯ V Test Conditions Ta ≤ 50°C, When 32.
Section 27 Electrical Characteristics Table 27.3 Permissible Output Current Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Permissible output low current (per pin) SCL1, SCL0, SDA1, SDA0 VCC = 4.0 V to 5.5 V IOL Output pins other than above ones Typ Max Unit ⎯ ⎯ 10 mA ⎯ ⎯ 1.
Section 27 Electrical Characteristics Table 27.4 Bus Driving Characteristics Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)* Objective pins: SCL1, SCL0, SDA1, and SDA0 Item Symbol Schmitt trigger input voltage VT – VT + + VT – VT – Min Typ Max Unit Test Conditions VCC × 0.3 ⎯ ⎯ V VCC = 4.0 V to 5.5 V ⎯ ⎯ VCC × 0.7 VCC = 4.0 V to 5.5 V 0.
Section 27 Electrical Characteristics 27.2.3 AC Characteristics Figure 27.6 shows the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 30 pF RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement levels • Low level: 0.8 V • High level: 2.0 V (VCC = 4.0 to 5.5 V) Figure 27.6 Output Load Circuit Rev. 6.00 Mar.
Section 27 Electrical Characteristics (1) Clock Timing Table 27.5 lists the clock timing. Table 27.5 Clock Timing Condition A: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 10 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 74 100 ns Figure 27.
Section 27 Electrical Characteristics (2) Control Signal Timing Table 27.6 lists the control signal timing. Table 27.6 Control Signal Timing Condition A: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 10 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item Symbol Min Min Unit Test Conditions RES setup time tRESS 250 ⎯ ns Figure 27.
Section 27 Electrical Characteristics (3) Bus Timing Table 27.7 lists the bus timing. Table 27.7 Bus Timing Condition A: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, φ = 10 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item Symbol Address delay time tAD ⎯ Address setup time tAS 0.5 × tcyc − 30 Address hold time tAH 0.
Section 27 Electrical Characteristics (4) Timing of On-Chip Peripheral Modules Table 27.8 lists the timing of on-chip peripheral modules. Table 27.8 Timing of On-Chip Peripheral Modules Condition A: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 10 to 13.
Section 27 Electrical Characteristics 2 Table 27.9 I C Bus Timing Conditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20°C to +75°C Standard Value Item Symbol Min Typ Max Unit Test Conditions SCL input cycle time tSCL 12 ⎯ ⎯ tcyc Figure 27.7 SCL input high pulse width tSCLH 3 ⎯ ⎯ tcyc SCL input low pulse width tSCLL 5 ⎯ ⎯ tcyc SCL, SDA input rise time tSr ⎯ ⎯ 7.
Section 27 Electrical Characteristics VIH SDA0 to SDA1 VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL0 to SCL1 P* S* tsf tSCLL tSCL Sr* tSr tSDAS tSDAH Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition 2 Figure 27.7 I C Bus Interface Input/Output Timing (Optional) Rev. 6.00 Mar.
Section 27 Electrical Characteristics 27.2.4 A/D Conversion Characteristics Table 27.10 lists the A/D conversion characteristics. Table 27.10 A/D Conversion Characteristics Condition A: VCC = 4.0 V to 5.5 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 10 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item Min Typ Max Unit Resolution 10 10 10 bits Conversion time 9.
Section 27 Electrical Characteristics 27.2.5 D/A Conversion Characteristics Table 27.11 lists the D/A conversion characteristics. Table 27.11 D/A Conversion Characteristics Condition A: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, φ = 10 to 13.
Section 27 Electrical Characteristics 27.2.6 Flash Memory Characteristics Table 27.12 Flash Memory Characteristics Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.
Section 27 Electrical Characteristics Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes (Shows the total period for which the P1 bit in the flash memory control register 1 (FLMCR1) is set. It does not include the program verification time.) 3. Erase block time (Shows the total period for which the E1 bit in FLMCR1 is set. It does not include the erase verification time.) 4.
Section 27 Electrical Characteristics 27.3 Electrical Characteristics of H8S/2239 Group 27.3.1 Absolute Maximum Ratings Table 27.13 lists the absolute maximum ratings. Table 27.13 Absolute Maximum Ratings Item Value Unit VCC –0.3 to +4.3 V CVCC –0.3 to +4.3 V Input voltage (except ports 4 and Vin 9) –0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V Reference power supply voltage Vref –0.3 to AVCC +0.3 V Analog power supply voltage AVCC –0.3 to +4.
Section 27 Electrical Characteristics 27.3.2 DC Characteristics Table 27.14 lists the DC characteristics. Table 27.15 lists the permissible output currents. Table 27.16 lists the bus driving characteristics. Table 27.14 DC Characteristics (1) Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C 1 (regular specifications)* Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.
Section 27 Electrical Characteristics Symbol Item Output high voltage Output low voltage Typ Max Unit VCC – 0.5 ⎯ ⎯ V VCC – 1.0 ⎯ ⎯ V VCC – 2.0 ⎯ ⎯ V IOH = –100 µA (reference value) ⎯ ⎯ 0.4 V ⎯ ⎯ 0.4 V IOL = 0.4 mA 2 I = 0.8 mA* ⎯ ⎯ 1.0 µA ⎯ ⎯ 1.0 µA ⎯ ⎯ 1.0 µA Vin = 0.2 to AVCC – 0.2 V | ITSI | ⎯ ⎯ 1.0 µA Vin = 0.2 to VCC – 0.
Section 27 Electrical Characteristics Table 27.14 DC Characteristics (2) Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C 1 (regular specifications)* Condition C (F-ZTAT version): VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 27 Electrical Characteristics Item Min Typ Max Unit Test Conditions ⎯ 70 180 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used Subsleep mode ⎯ 50 130 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used Watch mode ⎯ 8 40 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used Standby 3 mode* ⎯ 1.0 10 µA VCC = 3.0 V VCC = 3.6 V Ta ≤ 50°C, When 32.768 kHz crystal resonator is not used ⎯ ⎯ 50 µA VCC = 3.6 V 50°C < Ta, When 32.
Section 27 Electrical Characteristics Table 27.14 DC Characteristics (3) Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide1 range specifications)* Condition C (F-ZTAT version): Item Input capacitance VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 27 Electrical Characteristics Item Min Typ Max Unit Test Conditions ⎯ 15 ⎯ mA f = 20.0 MHz, VCC = 3.0 V (reference value) ⎯ 13 ⎯ mA f = 16.0 MHz, VCC = 3.0 V (reference value) Subactive mode ⎯ 45 180 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used Subsleep mode ⎯ 30 100 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used Watch mode ⎯ 8 40 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used Standby 3 mode* ⎯ 0.5 10 µA VCC = 3.0 V VCC = 3.
Section 27 Electrical Characteristics Table 27.15 Permissible Output Currents Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications) Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications) Ta = –40°C to +85°C (widerange specifications) Condition C (F-ZTAT version): VCC = 3.0 V to 3.
Section 27 Electrical Characteristics Table 27.16 Bus Driving Characteristics Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)*, Objective pins: SCL1, SCL0, SDA1, SDA0 Item Symbol – Schmitt trigger VT input voltage VT+ Min Typ Max Unit Test Conditions VCC × 0.3 ⎯ ⎯ V VCC = 2.7 V to 3.6 V ⎯ ⎯ VCC × 0.7 V VCC = 2.7 V to 3.6 V ⎯ ⎯ V VCC = 2.
Section 27 Electrical Characteristics 27.3.3 AC Characteristics Figure 27.8 shows the test conditions for the AC characteristics. 3V RL RL = 2.4 kΩ RH = 12 kΩ LSI output pin C C = 30 pF RH Input/output timing measurement levels • Low level: 0.8 V • High level: 2.0 V (VCC = 2.7 to 3.6 V) 1.5 V (VCC = 2.2 to 2.7 V) Figure 27.8 Output Load Circuit Rev. 6.00 Mar.
Section 27 Electrical Characteristics (1) Clock Timing Table 27.17 lists the clock timing. Table 27.17 Clock Timing Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 to 16.0 MHz, Ta = –20°C to +75°C (regular specifications) Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 to 6.
Section 27 Electrical Characteristics Condition A Condition B Condition C Item Symbol Min Typ Max Min Typ Max Min Typ Max Unit Oscillation stabilization time in software standby (crystal) tOSC2 8 ⎯ ⎯ 16 ⎯ ⎯ 8 ⎯ ⎯ ms 500 ⎯ ⎯ 1000 ⎯ ⎯ 500 ⎯ ⎯ µs 2 ⎯ ⎯ 4 ⎯ ⎯ 2 s External clock tDEXT output stabilization delay time Subclock oscillation stabilization time tOSC3 ⎯ ⎯ Subclock oscillator frequency fSUB ⎯ 32.768 ⎯ ⎯ 32.768 ⎯ ⎯ 32.
Section 27 Electrical Characteristics (2) Control Signal Timing Table 27.18 lists the control signal timing. Table 27.18 Control Signal Timing Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 to 16.0 MHz, Ta = –20°C to +75°C (regular specifications) Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 to 6.
Section 27 Electrical Characteristics (3) Bus Timing Table 27.19 lists the bus timing. Table 27.19 Bus Timing Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 16.0 MHz, Ta = –20°C to +75°C (regular specifications) Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 6.
Section 27 Electrical Characteristics Condition A Condition B Item Symbol Min Max Read data access time 2 tACC2 ⎯ 1.5 × tcyc ⎯ − 50 1.5 × tcyc ⎯ − 90 1.5 × tcyc ns − 40 Read data access time 3 tACC3 ⎯ 2.0 × tcyc ⎯ − 55 2.0 × tcyc ⎯ − 90 2.0 × tcyc ns − 50 Read data access time 4 tACC4 ⎯ 2.5 × tcyc ⎯ − 50 2.5 × tcyc ⎯ − 90 2.5 × tcyc ns − 40 Read data access time 5 tACC5 ⎯ 3.0 × tcyc ⎯ − 55 3.0 × tcyc ⎯ − 90 3.
Section 27 Electrical Characteristics (4) DMAC Timing Table 27.20 lists the DMAC timing. Table 27.20 DMAC Timing Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 16.0 MHz, Ta = –20°C to +75°C (regular specifications) Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 6.
Section 27 Electrical Characteristics (5) Timing of On-Chip Peripheral Modules 2 Table 27.21 lists the timing of on-chip peripheral modules. Table 27.22 lists the I C bus timing. Table 27.21 Timing of On-Chip Peripheral Modules Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 to 16.0 MHz, Ta = –20°C to +75°C (regular specifications) Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.
Section 27 Electrical Characteristics Condition A Item Symbol Min TMR Condition B Condition C Max Min Max Min Max Unit Test Conditions Timer output delay tTMOD time ⎯ 70 ⎯ 150 ⎯ 50 ns Figure 27.27 Timer reset input setup time tTMRS 50 ⎯ 80 ⎯ 30 ⎯ ns Figure 27.29 Timer clock input setup time tTMCS 50 ⎯ 80 ⎯ 30 ⎯ ns Figure 27.28 Timer clock pulse width Single edge tTMCWH 1.5 ⎯ 1.5 ⎯ 1.5 ⎯ tcyc Both edges tTMCWL 2.5 ⎯ 2.5 ⎯ 2.
Section 27 Electrical Characteristics 2 Table 27.22 I C Bus Timing Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20°C to +75°C Item Symbol Min Typ Max Unit Test Conditions SCL input cycle time tSCL 12 tcyc ⎯ ⎯ ns Figure 27.34 SCL input high pulse width tSCLH 3 tcyc ⎯ ⎯ ns SCL input low pulse width tSCLL 5 tcyc ⎯ ⎯ ns SCL, SDA input rise time tSr ⎯ ⎯ 7.
Section 27 Electrical Characteristics 27.3.4 A/D Conversion Characteristics Table 27.23 lists the A/D conversion characteristics. Table 27.23 A/D Conversion Characteristics Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V*, AVCC = 2.7 V to 3.6 V*, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 16.0 MHz, Ta = –20°C to +75°C (regular specifications) Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V*, AVCC = 2.2 V to 3.6 V*, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 6.
Section 27 Electrical Characteristics 27.3.5 D/A Conversion Characteristics Table 27.24 lists the D/A conversion characteristics. Table 27.24 D/A Conversion Characteristics Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 16.0 MHz, Ta = –20°C to +75°C (regular specifications) Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 6.
Section 27 Electrical Characteristics 27.3.6 Flash Memory Characteristics Table 27.25 lists the flash memory characteristics. Table 27.25 Flash Memory Characteristics Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, VCC = 3.0 V to 3.
Section 27 Electrical Characteristics Item Erase Symbol Min Typ Max Unit Wait time after SWE1 bit setting*1 tsswe 1 1 ⎯ µs Wait time after ESU1 bit setting*1 tsesu 100 100 ⎯ µs Wait time after E1 bit setting*1*5 tse 10 10 100 ms Wait time after E1 bit clear*1 tce 10 10 ⎯ µs Wait time after ESU1 bit clear*1 tcesu 10 10 ⎯ µs Wait time after EV1 bit setting*1 tsev 20 20 ⎯ µs Wait time after H'FF dummy write*1 tsevr 2 2 ⎯ µs Wait time after EV1 bit clear*1 tcev
Section 27 Electrical Characteristics 27.4 Electrical Characteristics of H8S/2238B and H8S/2236B 27.4.1 Absolute Maximum Ratings Table 27.26 lists the absolute maximum ratings. Table 27.26 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +7.0 V CVCC –0.3 to +4.3 V Input voltage (except ports 4 and 9) Vin –0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V Reference voltage Vref –0.3 to AVCC +0.
Section 27 Electrical Characteristics 27.4.2 DC Characteristics Table 27.27 lists the DC characteristics. Table 27.28 lists the permissible output currents. Table 27.29 lists the bus drive characteristics. Table 27.27 DC Characteristics (1) Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Condition B (Masked ROM version): VCC = 2.7 V to 5.
Section 27 Electrical Characteristics Item Symbol Min Typ Max Unit Test Conditions ⎯ ⎯ 0.4 V IOL = 0.4 mA ⎯ ⎯ 0.4 V IOL = 0.8 mA ⎯ ⎯ 1.0 µA STBY, NMI, MD2 to MD0, FWE ⎯ ⎯ 1.0 µA Vin = 0.5 to VCC – 0.5 V Ports 4, 9 ⎯ ⎯ 1.0 µA Vin = 0.5 to AVCC – 0.5 V Output low voltage All output 3 pins* VOL Input leakage current RES | Iin | Three-state leakage current (off state) Ports 1, 3, 7, A to G | ITSI | ⎯ ⎯ 1.0 µA Vin = 0.5 to VCC – 0.
Section 27 Electrical Characteristics Table 27.27 DC Characteristics (2) Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Item Input capacitance Symbol Min Typ Max Unit Test Conditions Cin ⎯ ⎯ 30 pF NMI ⎯ ⎯ 30 pF P32 to P35 ⎯ ⎯ 20 pF All input pins except the above ⎯ ⎯ 15 pF ⎯ 23 40 mA VCC = 3.0 V VCC = 5.5 V f = 13.
Section 27 Electrical Characteristics Item Symbol Min Typ Current Standby 2 3 dissipation* mode* ICC* ⎯ 1.0 10 µA VCC = 3.0 V VCC = 5.5 V Ta ≤ 50°C, When 32.768 kHz crystal resonator is not used ⎯ ⎯ 50 VCC = 5.5 V 50°C < Ta, When 32.768 kHz crystal resonator is not used ⎯ 0.3 1.5 mA ⎯ 0.01 5.0 µA ⎯ 1.3 3.5 mA ⎯ 0.01 5.0 µA 2.
Section 27 Electrical Characteristics Table 27.27 DC Characteristics (3) Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.
Section 27 Electrical Characteristics Item Symbol Min Typ Max Unit Analog power During A/D supply current and D/A conversion AlCC ⎯ 0.3 1.5 mA ⎯ 0.01 5.0 µA AlCC ⎯ 1.3 3.5 mA ⎯ 0.01 5.0 µA VRAM 2.0 ⎯ ⎯ V Idle Reference current During A/D and D/A conversion Idle RAM standby voltage Test Conditions Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 2.0 V and 5.
Section 27 Electrical Characteristics Table 27.28 Permissible Output Currents Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.
Section 27 Electrical Characteristics Table 27.29 Bus Drive Characteristics Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)* Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.
Section 27 Electrical Characteristics 27.4.3 AC Characteristics Figure 27.9 shows the test conditions for the AC characteristics. 3V RL LSI output pin C RH C = 30 pF RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement levels • Low level: 0.8 V • High level: 2.0 V Figure 27.9 Output Load Circuit Rev. 6.00 Mar.
Section 27 Electrical Characteristics (1) Clock Timing Table 27.30 lists the clock timing Table 27.30 Clock Timing Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 MHz to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 MHz to 13.
Section 27 Electrical Characteristics (2) Control Signal Timing Table 27.31 lists the control signal timing. Table 27.31 Control Signal Timing Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 MHz to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.
Section 27 Electrical Characteristics (3) Bus Timing Table 27.32 lists the bus timing. Table 27.32 Bus Timing Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 13.
Section 27 Electrical Characteristics Conditions A, B Item Symbol Min Max Unit Test Conditions WR delay time 1 tWRD1 ⎯ 50 ns WR delay time 2 tWRD2 ⎯ 50 ns Figures 27.14 to 27.18 WR pulse width 1 tWSW1 1.0 × tcyc – 30 ⎯ ns WR pulse width 2 tWSW2 1.5 × tcyc – 30 ⎯ ns Write data delay time tWDD ⎯ 70 ns Write data setup time tWDS 0.5 × tcyc – 37 ⎯ ns Write data hold time tWDH 0.
Section 27 Electrical Characteristics (4) Timing of On-Chip Peripheral Modules 2 Table 27.33 shows the timing of on-chip peripheral modules, and table 27.34 shows the I C bus timing. Table 27.33 Timing of On-Chip Peripheral Modules Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 MHz to 13.
Section 27 Electrical Characteristics Conditions A, B Item WDT1 BUZZ output delay time SCI* Input clock cycle A/D converter Note: * Asynchronous Symbol Min Max Unit Test Conditions tBUZD ⎯ 100 ns Figure 27.30 tScyc 4 ⎯ tcyc Figure 27.31 6 ⎯ Synchronous Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr ⎯ 1.5 tcyc Input clock fall time tSCKf ⎯ 1.
Section 27 Electrical Characteristics 2 Table 27.34 I C Bus Timing Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20°C to +75°C Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20°C to +75°C Conditions A, B Item Symbol Min Typ Max Unit Test Conditions SCL input cycle time tSCL 12 tcyc ⎯ ⎯ ns Figure 27.
Section 27 Electrical Characteristics 27.4.4 A/D Conversion Characteristics A/D converter characteristics for the F-ZTAT and masked ROM versions are shown in table 27.35. Table 27.35 A/D Conversion Characteristics (F-ZTAT and Masked ROM Versions) Condition: VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 13.
Section 27 Electrical Characteristics 27.4.6 Flash Memory Characteristics Table 27.37 lists the flash memory characteristics. Table 27.37 Flash Memory Characteristics Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, Vref = 3.
Section 27 Electrical Characteristics Item Erasing Symbol Min Typ Max Unit Wait time after SWE1 bit clearing tcswe 100 100 ⎯ µs Maximum number of erases* * N ⎯ ⎯ 100 Times 1 5 Test Conditions Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes (Indicates the total time during which the P1 bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3.
Section 27 Electrical Characteristics 27.5 Electrical Characteristics of H8S/2238R and H8S/2236R 27.5.1 Absolute Maximum Ratings Table 27.38 lists the absolute maximum ratings. Table 27.38 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +4.3 V CVCC –0.3 to +4.3 V Input voltage (except ports 4 and 9) Vin –0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V Reference power supply voltage Vref –0.3 to AVCC +0.
Section 27 Electrical Characteristics 27.5.2 DC Characteristics Table 27.39 lists the DC characteristics. Table 27.40 lists the permissible output currents. Table 27.41 lists the bus driving characteristics. Table 27.39 DC Characteristics (1) Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS =AVSS = 0 V, Ta = –20°C to +75°C (regular specifications) 1 Ta = –40°C to +85°C (wide-range specifications)* Condition B (F-ZTAT version): VCC = 2.2 V to 3.
Section 27 Electrical Characteristics Symbol Item Output high voltage Output low voltage Typ Max Unit VCC – 0.5 ⎯ ⎯ V VCC – 1.0 ⎯ ⎯ V VCC – 2.0 ⎯ ⎯ V IOH = –100 µA (reference value) ⎯ ⎯ 0.4 V IOL = 0.4 mA ⎯ ⎯ 0.4 V IOL = 0.8 mA* ⎯ ⎯ 1.0 µA ⎯ ⎯ 1.0 µA Vin = 0.2 to VCC – 0.2 V ⎯ ⎯ 1.0 µA Vin = 0.2 to AVCC – 0.2 V | ITSI | ⎯ ⎯ 1.0 µA Vin = 0.2 to VCC – 0.
Section 27 Electrical Characteristics Table 27.39 DC Characteristics (2) Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS =AVSS = 0 V, Ta = –20°C to +75°C (regular specifications) 1 Ta = –40°C to +85°C (wide-range specifications)* Condition B (F-ZTAT version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.
Section 27 Electrical Characteristics Item Watch mode Current 2 consumption* Symbol Min 4 ⎯ ICC* Standby 3 mode* Analog power During A/D supply current conversion AlCC Idle Typ Max Unit Test Conditions 8 40 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used ⎯ 1.0 10 µA VCC = 3.0 V VCC = 3.6 V Ta ≤ 50°C, When 32.768 kHz crystal resonator is not used ⎯ ⎯ 50 µA VCC = 3.6 V 50°C < Ta, When 32.768 kHz crystal resonator is not used ⎯ 0.5 1.5 mA ⎯ 0.01 5.0 µA 1.3 2.
Section 27 Electrical Characteristics Table 27.39 DC Characteristics (3) Condition C (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Item Input capacitance Symbol Min Typ Max Unit Test Conditions ⎯ ⎯ 30 pF ⎯ ⎯ 30 pF P32 to P35 ⎯ ⎯ 20 pF All input pins other than above ones ⎯ ⎯ 15 pF ⎯ 20 37 mA VCC = 3.0 V VCC = 3.6 V f = 13.
Section 27 Electrical Characteristics Item Subsleep Current 2 consumption* mode Symbol Min 4 ⎯ ICC* Typ Max Unit Test Conditions 30 100 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used 40 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used Watch mode ⎯ 8 Standby 3 mode* ⎯ 0.5 10 µA VCC = 3.0 V VCC = 3.6 V Ta ≤ 50°C, When 32.768 kHz crystal resonator is not used ⎯ ⎯ 50 µA VCC = 3.6 V 50°C < Ta, When 32.768 kHz crystal resonator is not used ⎯ 0.5 1.5 mA ⎯ 0.01 5.
Section 27 Electrical Characteristics Table 27.40 Permissible Output Currents Condition A (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS =AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS =AVSS = 0 V, Ta = –20°C to +75°C (regular specifications) Condition C (Masked ROM version): VCC = 2.2 V to 3.
Section 27 Electrical Characteristics Table 27.41 Bus Driving Characteristics Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)*, Objective pins: SCL1 and 0 and SDA1 and 0 Item Symbol – Schmitt trigger VT input voltage VT+ Min Typ Max Unit Test Conditions VCC × 0.3 ⎯ ⎯ V VCC = 2.7 V to 3.6 V ⎯ ⎯ VCC × 0.7 V VCC = 2.7 V to 3.6 V ⎯ ⎯ V VCC = 2.
Section 27 Electrical Characteristics Table 27.42 Clock Timing Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS =AVSS = 0 V, φ = 32.768 kHz, 2 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS =AVSS = 0 V, φ = 32.768 kHz, 2 to 6.
Section 27 Electrical Characteristics (2) Control Signal Timing Table 27.43 lists the control signal timing. Table 27.43 Control Signal Timing Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS =AVSS = 0 V, φ = 32.768 kHz, 2 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.
Section 27 Electrical Characteristics (3) Bus Timing Table 27.44 lists the bus timing. Table 27.44 Bus Timing Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS =AVSS = 0 V, φ = 2 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS =AVSS = 0 V, φ = 2 to 6.
Section 27 Electrical Characteristics Condition A Conditions B, C Item Symbol Min Max Min Max Unit Read data access time 2 tACC2 ⎯ 1.5 × tcyc − 65 ⎯ 1.5 × tcyc − 90 ns Read data access time 3 tACC3 ⎯ 2.0 × tcyc − 65 ⎯ 2.0 × tcyc − 90 ns Read data access time 4 tACC4 ⎯ 2.5 × tcyc − 65 ⎯ 2.5 × tcyc − 90 ns Read data access time 5 tACC5 ⎯ 3.0 × tcyc − 65 ⎯ 3.
Section 27 Electrical Characteristics (4) Timing of On-Chip Peripheral Modules 2 Table 27.45 lists the timing of on-chip peripheral modules. Table 27.46 lists the I C bus timing. Table 27.45 Timing of On-Chip Peripheral Modules Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS =AVSS = 0 V, φ = 32.768 kHz, 2 to 13.
Section 27 Electrical Characteristics Condition A Item Symbol Conditions B, C Min Max Min Max Unit Test Conditions tcyc Figure 27.28 Timer clock Single edge tTMCWH pulse width Both edges tTMCWL 1.5 ⎯ 1.5 ⎯ 2.5 ⎯ 2.5 ⎯ WDT_1 BUZZ output delay time tBUZD ⎯ 100 ⎯ 150 ns Figure 27.30 SCI* Input clock cycle tScyc 4 ⎯ 4 ⎯ tcyc Figure 27.31 6 ⎯ 6 ⎯ TMR Asynchronous Synchronous Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 tScyc Input clock rise time tSCKr ⎯ 1.
Section 27 Electrical Characteristics 2 Table 27.46 I C Bus Timing Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20°C to +75°C Item Symbol Min Typ Max Unit Test Conditions SCL input cycle time tSCL 12 tcyc ⎯ ⎯ ns Figure 27.34 SCL input high pulse width tSCLH 3 tcyc ⎯ ⎯ ns SCL input low pulse width tSCLL 5 tcyc ⎯ ⎯ ns SCL, SDA input rise time tSr ⎯ ⎯ 7.
Section 27 Electrical Characteristics 27.5.4 A/D Conversion Characteristics Table 27.47 lists the A/D conversion characteristics. Table 27.47 A/D Conversion Characteristics Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V*, AVCC = 2.7 V to 3.6 V*, Vref = 2.7 V to AVCC, VSS =AVSS = 0 V, φ = 2 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version): VCC = 2.2 V to 3.6 V*, AVCC = 2.2 V to 3.
Section 27 Electrical Characteristics 27.5.5 D/A Conversion Characteristics Table 27.48 lists the D/A conversion characteristics. Table 27.48 D/A Conversion Characteristics Condition A (F-ZTAT version and masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS =AVSS = 0 V, φ = 2 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.
Section 27 Electrical Characteristics 27.5.6 Flash Memory Characteristics Table 27.49 lists the flash memory characteristics. Table 27.49 Flash Memory Characteristics Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V,VCC = 3.0 V to 3.
Section 27 Electrical Characteristics Item Programming Erase Symbol Min Typ Max Unit Maximum programming count*1*4 N1 ⎯ ⎯ 6*4 Times N2 ⎯ ⎯ 994*4 Wait time after SWE1 bit setting*1 tsswe 1 1 ⎯ µs Wait time after ESU1 bit setting*1 tsesu 100 100 ⎯ µs Wait time after E1 bit setting*1*5 tse 10 10 100 ms Wait time after E1 bit clear*1 tce 10 10 ⎯ µs Wait time after ESU1 bit clear*1 tcesu 10 10 ⎯ µs Wait time after EV1 bit setting*1 tsev 20 20 ⎯ µs Wait time af
Section 27 Electrical Characteristics 27.6 Electrical Characteristics of H8S/2237 Group and H8S/2227 Group 27.6.1 Absolute Maximum Ratings Table 27.50 lists the absolute maximum ratings. Table 27.50 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage Program voltage* VCC –0.3 to +4.3 V VPP –0.3 to +13.5 V Input voltage (except ports4 and 9)Vin –0.3 to VCC +0.3 V Input voltage (ports 4 and 9) –0.3 to AVCC +0.3 V Vin Reference power supply voltage Vref –0.
Section 27 Electrical Characteristics 27.6.2 DC Characteristics Table 27.51 lists the DC characteristics. Table 27.52 lists the permissible output currents. Table 27.51 DC Characteristics (1) Conditions (ZTAT version and F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Conditions (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.
Section 27 Electrical Characteristics Item Input leakage current Three states leakage current (off) Test Conditions Symbol Min Typ Max Unit | Iin | ⎯ ⎯ 1.0 µA STBY, NMI, FWE, MD2 to MD0 ⎯ ⎯ 1.0 µA Ports 4, 9 ⎯ ⎯ 1.0 µA Vin = 0.5 to AVCC – 0.5 V*3 Vin = 0.2 to AVCC – 0.2 V*4 | ITSI | ⎯ ⎯ 1.0 µA Vin = 0.5 to VCC – 0.5 V*3 Vin = 0.2 to VCC – 0.2 V*4 –IP 10 ⎯ 300 µA Vin = 0V RES Ports 1, 3, 7, and A to G Input pull-up MOS Ports A to E current Vin = 0.5 to VCC – 0.
Section 27 Electrical Characteristics Table 27.51 DC Characteristics (2) Conditions (F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,Vref = 2.7 V to AVCC, VSS =AVSS = 0 V,Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Symbol Min Typ Max Unit Test Conditions Cin ⎯ ⎯ 30 pF Vin = 0 V NMI ⎯ ⎯ 30 pF f = 1 MHz All input pins other than above ones ⎯ ⎯ 15 pF Ta = 25 °C ⎯ 20 37 mA VCC = 3.0 V VCC = 3.6 V f = 13.
Section 27 Electrical Characteristics Symbol Item Current Standby 2 3 consumption* mode* Analog power During A/D supply current conversion AlCC Idle Reference During A/D power supply conversion current Idle AlCC RAM standby voltage VRAM Max Unit Test Conditions Min Typ ⎯ 1.0 10 µA VCC = 3.0 V VCC = 3.6 V Ta ≤ 50°C, When 32.768 kHz crystal resonator is not used ⎯ ⎯ 50 µA VCC = 3.6 V 50°C < Ta, When 32.768 kHz crystal resonator is not used ⎯ 0.8 1.5 mA AVCC = 3.0 V ⎯ 0.01 5.
Section 27 Electrical Characteristics Table 27.51 DC Characteristics (3) Conditions (ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Symbol Min Typ Max Unit Test Conditions Cin ⎯ ⎯ 80 pF Vin = 0 V NMI ⎯ ⎯ 50 pF f = 1 MHz All input pins other than above ones ⎯ ⎯ 15 pF Ta = 25 °C ⎯ 16 28 mA VCC = 3.0 V VCC = 3.
Section 27 Electrical Characteristics Symbol Item Current Standby 2 3 consumption* mode* Analog power During A/D supply current conversion AlCC Idle Reference During A/D power supply conversion current Idle AlCC RAM standby voltage VRAM Test Conditions Min Typ Max Unit ⎯ 0.01 5.0 µA Ta ≤ 50°C, When 32.768 kHz crystal resonator is not used ⎯ ⎯ 20.0 µA 50°C < Ta, When 32.768 kHz crystal resonator is not used ⎯ 0.2 1.0 mA AVCC = 3.0 V ⎯ 0.01 5.0 µA ⎯ 1.3 2.5 mA ⎯ 0.01 5.
Section 27 Electrical Characteristics Table 27.51 DC Characteristics (4) Conditions (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Input capacitance Test Conditions Symbol Min Typ Max Unit Cin ⎯ ⎯ 80 pF NMI ⎯ ⎯ 50 pF All input pins other than above ones ⎯ ⎯ 15 pF ⎯ 20 37 mA VCC = 3.0 V VCC = 3.6 V f = 13.
Section 27 Electrical Characteristics Symbol Test Conditions Min Typ Max Unit ⎯ 35 90 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used Watch mode ⎯ 8 40 µA VCC = 3.0 V, When 32.768 kHz crystal resonator is used Standby 3 mode* ⎯ 0.01 10 µA VCC = 3.0 V VCC = 3.6 V Ta ≤ 50°C, When 32.768 kHz crystal resonator is not used ⎯ ⎯ 50 µA VCC = 3.6 V 50°C < Ta, When 32.768 kHz crystal resonator is not used ⎯ 0.8 1.5 mA AVCC = 3.0 V ⎯ 0.01 5.0 µA ⎯ 1.3 2.5 mA ⎯ 0.01 5.
Section 27 Electrical Characteristics Table 27.52 Permissible Output Currents Conditions (ZTAT version and F-ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Conditions (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.
Section 27 Electrical Characteristics 27.6.3 AC Characteristics Figure 27.9 shows the test conditions for the AC characteristics. (1) Clock Timing Table 27.53 lists the clock timing. Table 27.53 Clock Timing Condition A (ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version, masked ROM version): VCC = 2.
Section 27 Electrical Characteristics Condition A Condition B Condition C Item Symbol Min Max Min Max Min Max Unit Test Conditions External clock output stabilization delay time tDEXT 500 ⎯ 500 ⎯ 1000 ⎯ µs Figure 27.11 Subclock oscillation stabilization time tOSC3 ⎯ 2 ⎯ 2 ⎯ 3 s Subclock oscillator frequency fSUB 32.768 32.768 32.768 32.768 32.768 32.768 kHz Subclock (φSUB) cycle time tSUB 30.5 30.5 Rev. 6.00 Mar. 18, 2010 Page 938 of 982 REJ09B0054-0600 30.5 30.
Section 27 Electrical Characteristics (2) Control Signal Timing Table 27.54 lists the control signal timing. Table 27.54 Control Signal Timing Condition A (ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version, masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.
Section 27 Electrical Characteristics (3) Bus Timing Table 27.55 lists the bus timing. Table 27.55 Bus Timing Condition A (ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version, masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 13.
Section 27 Electrical Characteristics Condition B Condition A Max Symbol Min Max Read data access time 1 tACC1 ⎯ 1.0 × tcyc − ⎯ 65 1.0 × tcyc − ⎯ 65 1.0 × tcyc − ns 90 Read data access time 2 tACC2 ⎯ 1.5 × tcyc − ⎯ 65 1.5 × tcyc − ⎯ 65 1.5 × tcyc − ns 90 Read data access time 3 tACC3 ⎯ 2.0 × tcyc − ⎯ 65 2.0 × tcyc − ⎯ 65 2.0 × tcyc − ns 90 Read data access time 4 tACC4 ⎯ 2.5 × tcyc − ⎯ 65 2.5 × tcyc − ⎯ 65 2.5 × tcyc − ns 90 Read data access time 5 tACC5 ⎯ 3.
Section 27 Electrical Characteristics (4) Timing of On-Chip Peripheral Modules Table 27.56 lists the timing of on-chip peripheral modules. Table 27.56 Timing of On-Chip Peripheral Modules Condition A (ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V,φ = 32.768 kHz, 2 to 10 MHz,Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version, masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.
Section 27 Electrical Characteristics Condition A Item TMR Symbol Min Condition B Condition C Max Min Max Min Max Test Unit Conditions Timer output delay tTMOD time ⎯ 100 ⎯ 100 ⎯ 150 ns Figure 27.27 Timer reset input setup time tTMRS 50 ⎯ 50 ⎯ 80 ⎯ ns Figure 27.29 Timer clock input setup time tTMCS 50 ⎯ 50 ⎯ 80 ⎯ ns Figure 27.28 Timer clock Single edge tTMCWH 1.5 ⎯ 1.5 ⎯ 1.5 ⎯ tcyc pulse width Both edges tTMCWL 2.5 ⎯ 2.5 ⎯ 2.
Section 27 Electrical Characteristics 27.6.4 A/D Conversion Characteristics Table 27.57 lists the A/D conversion characteristics. Table 27.57 A/D Conversion Characteristics Condition A (ZTAT version): VCC = 2.7 V to 3.6 V*, AVCC = 2.7 V to 3.6 V*, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version, Masked ROM version): VCC = 2.7 V to 3.6 V*, AVCC = 2.7 V to 3.6 V*, Vref = 2.
Section 27 Electrical Characteristics 27.6.5 D/A Conversion Characteristics Table 27.58 lists the D/A conversion characteristics. Table 27.58 D/A Conversion Characteristics Condition A (ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (Masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.
Section 27 Electrical Characteristics 27.6.6 Flash Memory Characteristics Table 27.59 lists the flash memory characteristics. Table 27.59 Flash Memory Characteristics Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, VCC = 3.0 V to 3.
Section 27 Electrical Characteristics Item Erase Symbol Min Typ Max Unit Wait time after SWE1 bit setting*1 tsswe 1 1 ⎯ µs Wait time after ESU1 bit setting*1 tsesu 100 100 ⎯ µs Wait time after E1 bit setting*1*5 tse 10 10 100 ms Wait time after E1 bit clear*1 tce 10 10 ⎯ µs Wait time after ESU1 bit clear*1 tcesu 10 10 ⎯ µs Wait time after EV1 bit setting*1 tsev 20 20 ⎯ µs Wait time after H'FF dummy write*1 tsevr 2 2 ⎯ µs Wait time after EV1 bit clear*1 tcev 4
Section 27 Electrical Characteristics 27.7 Operating Timing 27.7.1 Clock Timing The clock timing is shown below. tcyc φ tCH tCf tCL tCr Figure 27.10 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 27.11 Oscillation Stabilization Timing Rev. 6.00 Mar.
Section 27 Electrical Characteristics 27.7.2 Control Signal Timing The control signal timing is shown below. φ tRESS tRESS tMRESS tMRESS RES tRESW MRES tMRESW Figure 27.12 Reset Input Timing φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ edge input tIRQS IRQ level input Figure 27.13 Interrupt Input Timing Rev. 6.00 Mar.
Section 27 Electrical Characteristics 27.7.3 Bus Timing Figures 27.14 to 27.19 show the bus timing. T1 T2 φ tAD A23 to A0 tAS tAH tCSD CS7 to CS0 tASD tASD AS tRSD1 RD (read) tRSD2 tACC2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 tWRD2 HWR, LWR (write) tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Figure 27.14 Basic Bus Timing (Two-State Access) Rev. 6.00 Mar.
Section 27 Electrical Characteristics T1 T2 T3 φ tAD A23 to A0 tAS tAH tCSD CS7 to CS0 tASD tASD AS tRSD1 RD (read) tRSD2 tACC4 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 27.15 Basic Bus Timing (Three-State Access) Rev. 6.00 Mar.
Section 27 Electrical Characteristics T1 T2 Tw tWTS tWTH tWTS tWTH T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) WAIT Figure 27.16 Basic Bus Timing (Three-State Access with One Wait State) Rev. 6.00 Mar.
Section 27 Electrical Characteristics T1 T2 or T3 T1 T2 φ tAD A23 to A0 tAS tAH CS0 AS tASD tASD tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 27.17 Burst ROM Access Timing (Two-State Access) Rev. 6.00 Mar.
Section 27 Electrical Characteristics T1 T2 or T3 T1 φ tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 27.18 Burst ROM Access Timing (One-State Access) φ tBRQS tBRQS BREQ tBACD tBACD BACK A23 to A0, CS7 to CS0, AS, RD, HWR, LWR tBZD Figure 27.19 External Bus Release Timing Rev. 6.00 Mar.
Section 27 Electrical Characteristics T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 DACK1, DACK0 Figure 27.20 DMAC Single Address Transfer Timing (Two-State Access) Rev. 6.00 Mar.
Section 27 Electrical Characteristics T1 T2 T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 DACK1, DACK0 Figure 27.21 DMAC Single Address Transfer Timing (Three-State Access) Rev. 6.00 Mar.
Section 27 Electrical Characteristics T1 T2 or T3 φ tTED tTED TEND1, TEND0 Figure 27.22 DMAC TEND Output Timing φ tDRQS tDRQH DREQ1, DREQ0 Figure 27.23 DMAC DREQ Input Timing 27.7.4 Timing of On-Chip Peripheral Modules Figures 27.24 to 27.34 show the timing of on-chip peripheral modules. T2 T1 φ tPRS tPRH Ports 1, 3, 4, 7, 9, A to G (read) tPWD Ports 1, 3, 7, A to G (write) Figure 27.24 I/O Port Input/Output Timing Rev. 6.00 Mar.
Section 27 Electrical Characteristics φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA5 to TIOCA0, TIOCB5 to TIOCB0, TIOCC3, TIOCC0, TIOCD3, TIOCD0 TIOCA5 to TIOCA3, TIOCB5 to TIOCB3, TIOCC3 and TIOCD3 are not available in the H8S/2227 Group. Figure 27.25 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 27.26 TPU Clock Input Timing φ tTMOD TMO3 to TMO0* Note: * TMO0 and TMO1 for the H8S/2237 Group and H8S/2227 Group. Figure 27.
Section 27 Electrical Characteristics φ tTMCS tTMCS TMCI23*, TMCI01 tTMCWL tTMCWH Note: * Not available in the H8S/2237 Group and H8S/2227 Group. Figure 27.28 8-Bit Timer Clock Input Timing φ tTMRS TMCI23*, TMCI01 Note: * Not available in the H8S/2237 Group and H8S/2227 Group Figure 27.29 8-Bit Timer Reset Input Timing φ tBUZD tBUZD BUZZ Figure 27.30 WDT_1 Output Timing tSCKW tSCKr tSCKf SCK3 to SCK0* tScyc Note: * SCK2 is not aveilable in the H8S/2227 Group. Figure 27.
Section 27 Electrical Characteristics SCK3 to SCK0* tTXD TxD3 to TxD0* (transmit data) tRXS tRXH RxD3 to RxD0* (receive data) Note: * SCK2, TxD2, and RxD2 are not available in the H8S/2227 Group. Figure 27.32 SCI Input/Output Timing (Clocked Synchronous Mode) φ tTRGS ADTRG Figure 27.
Section 27 Electrical Characteristics 27.8 Usage Note Though the F-ZTAT version and the masked ROM version satisfy electrical characteristics described in this manual, the actual value of electrical characteristics, operating margin, and noise margin may differ due to the differences of production process, on-chip ROM, and layout patterning.
Section 27 Electrical Characteristics Rev. 6.00 Mar.
Appendix A I/O Port States in Each Pin State Appendix A I/O Port States in Each Pin State A.
Appendix A I/O Port States in Each Pin State Pin Name MCU Operating Power-On Manual Reset Reset Mode Hardware Standby Mode Software Standby Mode, Watch Mode Bus Mastership Release State Program Execution State, Sleep Mode, Subsleep Mode Port 3 4 to 7 T keep T keep keep I/O port Port 4 4 to 7 T T T T T Input port P77 to P74 4 to 7 T keep T keep keep I/O port P73/TMO1/ TEND1*3/CS7 7 T keep T keep keep I/O port 4 to 6 T keep T [DDR ⋅ OPE = 0] T T P72/TMO0/ TEND0*3/C
Appendix A I/O Port States in Each Pin State Pin Name MCU Operating Power-On Manual Reset Reset Mode Hardware Standby Mode Software Standby Mode, Watch Mode Bus Mastership Release State Program Execution State, Sleep Mode, Subsleep Mode Port B 7 Port Name T keep T keep keep I/O port When 4, 5 the address output is 6 selected by the AEn bit L keep T [OPE = 0] T T Address output When a 4 to 6 port is selected T*1 keep T keep keep I/O port L keep T [OPE = 0] T T Address outpu
Appendix A I/O Port States in Each Pin State Pin Name MCU Operating Power-On Manual Reset Reset Mode Hardware Standby Mode PF7/φ 4 to 6 T Port Name Clock output [DDR = 0] Input port [DDR = 1] Clock output 7 PF6/AS 4 to 6 T H keep H T T PF5/RD PF2/WAIT PF1/BACK/ BUZZ [DDR = 0] Input port [DDR = 0] Input port [DDR = 0] Input port [DDR = 1] H [DDR = 1] [DDR = 1] Clock output Clock output [DDR = 0] Input port [DDR = 0] Input port [DDR = 1] H [DDR = 1] [DDR = 1] Clock output Clock o
Appendix A I/O Port States in Each Pin State Port Name Pin Name PF0/BREQ/ IRQ2 MCU Operating Power-On Manual Reset Reset Mode Hardware Standby Mode 4 to 6 T T keep Software Standby Mode, Watch Mode Bus Mastership Release State [BRLE = 0] keep T [BRLE = 1] T PG4/CS0 7 T keep T keep keep I/O port 4, 5 H keep T T 6 T [DDR ⋅ OPE = 0] T [DDR = 0] I/O port [DDR = 1] CS0 (H in sleep mode and subsleep mode.
Appendix B Product Codes Appendix B Product Codes Table B.
Appendix B Product Codes Table B.
Appendix B Product Codes Table B.
Appendix B Product Codes Package Product Type H8S/2236B Masked 5-V version Product Code Mark Code (Package Code) HD6432236B HD6432236B(***)TE 100-pin TQFP (TFP-100B) HD6432236B(***)TF 100-pin TQFP (TFP-100G) HD6432236B(***)F 100-pin QFP (FP-100A) HD6432236B(***)FA 100-pin QFP (FP-100B) HD6432236BW(***)TE 100-pin TQFP (TFP-100B) HD6432236BW(***)TF 100-pin TQFP (TFP-100G) HD6432236BW(***)F 100-pin QFP (FP-100A) HD6432236BW(***)FA 100-pin QFP (FP-100B) HD6432236R(***)TE 100-pin TQFP (TF
Appendix B Product Codes Table B.
Appendix C Package Dimensions Appendix C Package Dimensions JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Appendix C Package Dimensions JEITA Package Code P-TQFP100-12x12-0.40 RENESAS Code PTQP0100LC-A Previous Code TFP-100G/TFP-100GV MASS[Typ.] 0.4g HD *1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D 75 51 76 50 HE b1 26 Terminal cross section ZE 100 1 25 Index mark F c θ A S A2 ZD Reference Symbol c c1 *2 E bp *3 bp L A1 e x L1 M Detail F y S Figure C.2 TFP-100G Package Dimensions Rev. 6.00 Mar.
Appendix C Package Dimensions JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JE-B Previous Code FP-100A/FP-100AV MASS[Typ.] 1.7g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Appendix C Package Dimensions JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HD *1 D 75 51 76 50 bp c c1 HE *2 E b1 Reference Symbol ZE Terminal cross section 26 100 1 25 θ c F A2 A ZD L A1 S L1 Detail F e *3 y S bp x M Figure C.4 FP-100B Package Dimensions Rev. 6.00 Mar.
Appendix C Package Dimensions JEITA Package Code P-LFBGA112-10x10-0.80 RENESAS Code PLBG0112GA-A Previous Code BP-112/BP-112V MASS[Typ.] 0.3g D w S B E w S A ×4 v y1 S y A1 A S S e ZD A L K e J H B G Reference Symbol Dimension in Millimeters Min Nom Max D 10.00 F E 10.00 E v D w 0.20 A 1.40 ZE C B A1 0.15 0.35 e A b 1 2 3 4 5 φ b 6 7 φ 8 9 10 11 0.40 0.45 0.80 0.45 0.50 0.55 x 0.08 y 0.10 y1 0.2 SD ×M S A B SE ZD 1.00 ZE 1.
Appendix C Package Dimensions JEITA Package Code T-TFBGA112-10x10-0.80 RENESAS Code TTBG0112GA-A Previous Code TBP-112A/TBP-112AV MASS[Typ.] 0.2g D w S B E w S A ×4 v y1 S y A1 A S S e ZD A L e K J H B G Reference Symbol Dimension in Millimeters Min Nom Max D 10.00 F E 10.00 E v D w 0.30 A 1.20 ZE C B A1 0.20 0.35 A b 1 2 3 4 5 6 φ b 7 φ 8 9 ×M S A B 10 11 0.45 0.45 0.50 0.55 x 0.08 y 0.10 y1 0.2 SD SE ZD 1.00 ZE 1.00 Figure C.
Index Index 16-Bit Timer Pulse Unit.......................... 359 A/D Conversion Time............................. 699 A/D Converter ........................................ 689 A/D Converter Activation....................... 426 Absolute Address...................................... 91 ABWCR.................................. 812, 823, 834 Activation by Software ........................... 301 ADCR ............................. 695, 816, 828, 838 ADCSR ........................... 693, 816, 828, 838 ADDR ..
Index framing error ...........................................592 Free-running count operation ..................399 General Registers ......................................72 2 I C bus format .........................................653 2 I C Bus Interface .....................................633 ICCR ............................... 644, 815, 827, 836 ICDR ............................... 637, 815, 827, 837 ICMR ...................................... 640, 827, 837 ICMR/SAR.................................
Index PORT9 .................................... 817, 828, 838 PORTA ................................... 817, 828, 838 PORTB ................................... 817, 828, 838 PORTC ................................... 817, 828, 838 PORTD ................................... 817, 828, 838 PORTE.................................... 817, 829, 838 PORTF.................................... 817, 829, 838 PORTG ................................... 817, 829, 838 Program Counter.......................................
Index TGI3B .....................................................424 TGI3C .....................................................424 TGI3D .....................................................424 TGI4A .....................................................424 TGI4B .....................................................424 TGI5A .....................................................424 TGI5B .....................................................424 TGR................................. 396, 813, 825, 835 TIER....
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2258, H8S/2239, H8S/2238, H8S/2237, H8S/2227 Groups Publication Date: 1st Edition, September 2002 Rev.6.00, March 18, 2010 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2010. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8S/2258, H8S/2239, H8S/2238, H8S/2237, H8S/2227 Groups Hardware Manual REJ09B0054-0600
