Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 856 of 982
REJ09B0054-0600
(3) Bus Timing
Table 27.7 lists the bus timing.
Table 27.7 Bus Timing
Condition A: V
CC
= 4.0 V to 5.5 V, AV
CC
= 4.0 V to 5.5 V, V
ref
= 4.0 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 10 to 13.5 MHz, T
a
= –20°C to +75°C (regular specifications), T
a
= –40°C to
+85°C (wide-range specifications)
Condition A
Item Symbol
Min Max
Unit Test Conditions
Address delay time t
AD
⎯ 50 ns
Address setup time t
AS
0.5 × t
cyc
− 30 ⎯ ns
Figures 27.14 to
27.18
Address hold time t
AH
0.5 × t
cyc
− 15 ⎯ ns
CS delay time t
CSD
⎯ 50 ns
AS delay time t
ASD
⎯ 50 ns
RD delay time 1 t
RSD1
⎯ 50 ns
RD delay time 2 t
RSD2
⎯ 50 ns
Read data setup time t
RDS
30 ⎯ ns
Read data hold time t
RDH
0 ⎯ ns
Read data access time 1 t
ACC1
⎯ 1.0 × t
cyc
− 65 ns
Read data access time 2 t
ACC2
⎯ 1.5 × t
cyc
− 65 ns
Read data access time 3 t
ACC3
⎯ 2.0 × t
cyc
− 65 ns
Read data access time 4 t
ACC4
⎯ 2.5 × t
cyc
− 65 ns
Read data access time 5 t
ACC5
⎯ 3.0 × t
cyc
− 65 ns
WR delay time 1 t
WRD1
⎯ 50 ns
WR delay time 2 t
WRD2
⎯ 50 ns
WR pulse width 1 t
WSW1
1.0 × t
cyc
− 30 ⎯ ns
WR pulse width 2 t
WSW2
1.5 × t
cyc
− 30 ⎯ ns
Write data delay time t
WDD
⎯ 70 ns
Write data setup time t
WDS
0.5 × t
cyc
− 37 ⎯ ns
Write data hold time t
WDH
0.5 × t
cyc
− 15 ⎯ ns
WAIT setup time t
WTS
50 ⎯ ns
WAIT hold time t
WTH
10 ⎯ ns
Figure 27.16
BREQ setup time t
BRQS
50 ⎯ ns
BACK delay time t
BACD
⎯ 50 ns
Figure 27.19
Bus-floating time t
BZD
⎯ 80 ns