Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 633 of 982
REJ09B0054-0600
Section 16 I
2
C Bus Interface (IIC) (Option)
An I
2
C bus interface is available as an option. Observe the following notes when using this option.
1. For masked ROM versions, a W is added to the part number in products in which this optional
function is used.
Examples: HD6432239WTE
The H8S/2258 Group, H8S/2239 Group, and H8S/2238 Group have an internal I
2
C bus
interface of two channels.
The I
2
C bus interface conforms to and provides a subset of the Philips I
2
C bus (inter-IC bus)
interface functions. The register configuration that controls the I
2
C bus differs partly from the
Philips configuration, however.
The I
2
C bus interface data transfer is performed using a data line (SDA) and a clock line (SCL) for
each channel, which allows efficient use of connectors and the area of the PCB.
Notes: 1. An I
2
C bus interface is not available in the H8S/2237 Group and H8S/2227 Group.
2. When the power supply voltage ranges from 2.2 V to 2.7 V, the I
2
C bus interface is not
available.
16.1 Features
• Selection of I
2
C bus format or clocked synchronous serial format
⎯ I
2
C bus format: addressing format with acknowledge bit, for master/slave operation
⎯ Clocked synchronous serial format: non-addressing format without acknowledge bit, for
master operation only
I
2
C bus format
• Two ways of setting slave address
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Wait function in master mode
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
IFIIC05C_000020020700