Datasheet

Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 582 of 982
REJ09B0054-0600
Bit Bit Name
Initial
Value R/W Description
2
1
0
ACS2
ACS1
ACS0
0
0
0
R/W
R/W
R/W
Asynchronous Clock Source Select
When an average transfer rate is selected, the
base clock is set automatically regardless of the
ABCS value. Note that average transfer rates are
not supported for operating frequencies other than
10.667 MHz and 16 MHz.
The ACS0 to ACS0 settings are valid when the
external clock input is selected (CKE in SCR = 0)
in asynchronous mode (C/A in SMR = 0).
000: External clock input
001: Selects the average transfer rate 115.152
kbps only for φ = 10.667 MHz (operates on a
base clock with a frequency of 16 times the
transfer rate).
010: Selects the average transfer rate 460.606
kbps only for φ = 10.667 MHz (operates on a
base clock with a frequency of 8 times the
transfer rate).
011: Reserved
100: TPU clock input (logical AND of TIOCA1 and
TIOCA2)
101: Selects the average transfer rate 115.196
kbps only for φ = 16 MHz (operates on a
base clock with a frequency of 16 times the
transfer rate).
110: Selects the average transfer rate 460.784
kbps only for φ = 16 MHz (operates on a
base clock with a frequency of 16 times the
transfer rate).
111: Selects the average transfer rate 720 kbps
only for φ = 16 MHz (operates on a base
clock with a frequency of 8 times the transfer
rate).
Figures 15.3 and 15.4 show an example of the internal base clock when the average transfer rate is
selected.