Datasheet

Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 559 of 982
REJ09B0054-0600
Bit Bit Name
Initial
Value R/W Description
3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For
details, refer to section 15.5, Multiprocessor
Communication Function.
When receive data including MPB = 0 is received,
receive data transfer from RSR to RDR, receive
error detection, and setting of the RERF, FER, and
ORER flags in SSR, are not performed.
When receive data including MPB = 1 is received,
the MPB bit in SSR is set to 1, the MPIE bit is
cleared to 0 automatically, and generation of RXI
and ERI interrupts (when the TIE and RIE bits in
SCR are set to 1) and FER and ORER flag setting
are enabled.
2 TEIE 0 R/W Transmit End Interrupt Enable
This bit is set to 1, TEI interrupt request is enabled.
TEI cancellation can be performed by reading 1
from the DRE flag in SSR, then clearing it to 0 and
clearing the TEND flag to 0, or clearing the TEIE
bit to 0.