Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 922 of 982
REJ09B0054-0600
Table 27.46 I
2
C Bus Timing
Conditions: V
CC
= 2.7 V to 3.6 V, V
SS
= 0 V, φ = 5 MHz to maximum operating frequency,
T
a
= –20°C to +75°C
Item Symbol Min Typ Max Unit Test
Conditions
SCL input cycle time t
SCL
12 t
cyc
⎯ ⎯ ns Figure 27.34
SCL input high pulse width t
SCLH
3 t
cyc
⎯ ⎯ ns
SCL input low pulse width t
SCLL
5 t
cyc
⎯ ⎯ ns
SCL, SDA input rise time t
Sr
⎯ ⎯ 7.5 t
cyc
*
ns
SCL, SDA input fall time t
Sf
⎯ ⎯ 300 ns
SCL, SDA input spike pulse
delete time
t
SP
⎯ ⎯ 1 t
cyc
ns
SDA input bus free time t
BUF
5 t
cyc
⎯ ⎯ ns
Operating condition input hold
time
t
STAH
3 t
cyc
⎯ ⎯ ns
Retransmitting operating
condition input setup time
t
STAS
3 t
cyc
⎯ ⎯ ns
Stop condition input setup time t
STOS
3 t
cyc
⎯ ⎯ ns
Data input setup time t
SDAS
0.5 t
cyc
⎯ ⎯ ns
Data input hold time t
SDAH
0 ⎯ ⎯ ns
SCL, SDA capacitor load C
b
⎯ ⎯ 400 pF
Note: * Maximum SCL and SDA input rise time 7.5 t
cyc
or 17.5 t
cyc
can be selected depending on
the clock that is used in the I
2
C module. For detail, see section 16.6, Usage Notes.