Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 899 of 982
REJ09B0054-0600
(3) Bus Timing
Table 27.32 lists the bus timing.
Table 27.32 Bus Timing
Condition A (F-ZTAT version): V
CC
= 3.0 V to 5.5 V, AV
CC
= 3.6 V to 5.5 V,
V
ref
= 3.6 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 2 MHz to 13.5 MHz,
T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Condition B (Masked ROM version): V
CC
= 2.7 V to 5.5 V, AV
CC
= 3.6 V to 5.5 V,
V
ref
= 3.6 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 2 MHz to 13.5 MHz,
T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Conditions A, B
Item Symbol Min Max Unit Test Conditions
Address delay time t
AD
⎯ 50 ns
Address setup time t
AS
0.5 × t
cyc
– 30 ⎯ ns
Address hold time t
AH
0.5 × t
cyc
– 15 ⎯ ns
CS delay time t
CSD
⎯ 50 ns
Figures 27.14 to
27.18
AS delay time t
ASD
⎯ 50 ns
RD delay time 1 t
RSD1
⎯ 50 ns
RD delay time 2 t
RSD2
⎯ 50 ns
Read data setup time t
RDS
30 ⎯ ns
Read data hold time t
RDH
0 ⎯ ns
Read data access time 1 t
ACC1
⎯ 1.0 × t
cyc
– 65 ns
Read data access time 2 t
ACC2
⎯ 1.5 × t
cyc
– 65 ns
Read data access time 3 t
ACC3
⎯ 2.0 × t
cyc
– 65 ns
Read data access time 4 t
ACC4
⎯ 2.5 × t
cyc
– 65 ns
Read data access time 5 t
ACC5
⎯ 3.0 × t
cyc
– 65 ns