Datasheet

Section 24 Power-Down Modes
Rev. 6.00 Mar. 18, 2010 Page 799 of 982
REJ09B0054-0600
24.9 Subactive Mode
24.9.1 Transition to Subactive Mode
When the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR = 1,
the DTON bit in LPWRCR = 1, the LSON bit = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, CPU
operation shifts to subactive mode. When an interrupt occurs in watch mode, and if the LSON bit
of LPWRCR is 1, a transition is made to subactive mode. And if an interrupt occurs in subsleep
mode, a transition is made to subactive mode.
In subactive mode, the CPU operates at low speed on the subclock, and the program is executed
step by step. Peripheral modules other than PBC, TMR_0 to TMR_3, WDT_0, and WDT_1, and
system clock oscillator are also stopped.
When operating the CPU in subactive mode, the SCKCR SCK2 to SCK0 bits must be set to 0.
24.9.2 Exiting Subactive Mode
Subactive mode is exited by the SLEEP instruction or the RES, MRES or STBY pin.
• Exiting Subactive Mode by SLEEP Instruction
When the SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the DTON bit in
LPWRCR = 0, and the PSS bit in TCSR_1 (WDT_1) = 1, the CPU exits subactive mode and a
transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit
in SBYCR = 0, the LSON bit in LPWRCR = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, a
transition is made to subsleep mode. Finally, when the SLEEP instruction is executed with the
SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit = 0, and the PSS bit in
TCSR_1 (WDT_1) = 1, a direct transition is made to high-speed mode (SCK2 to SCK0 all 0).
• Exiting Subactive Mode by RES Pin or MRES Pin
For exiting subactive mode by the RES or MRES pin, see section 24.4.2, Clearing Software
Standby Mode.
• Exiting Subactive Mode by STBY Pin
When the STBY pin level is driven low, a transition is made to hardware standby mode.