Datasheet

Section 24 Power-Down Modes
Rev. 6.00 Mar. 18, 2010 Page 795 of 982
REJ09B0054-0600
24.5 Hardware Standby Mode
24.5.1 Transition to Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
Do not change the state of the mode pins (MD2 to MD0) while this LSI is in hardware standby
mode.
24.5.2 Clearing Hardware Standby Mode
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY
pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.
Ensure that the RES pin is held low until the clock oscillator settles (at least tosc1 ms—the
oscillation settling time—when using a crystal oscillator). When the RES pin is subsequently
driven high, a transition is made to the program execution state via the reset exception handling
state.
24.5.3 Hardware Standby Mode Timing
Figure 24.4 shows an example of hardware standby mode timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting
for the oscillation settling time, then changing the RES pin from low to high.