Datasheet

Section 24 Power-Down Modes
Rev. 6.00 Mar. 18, 2010 Page 793 of 982
REJ09B0054-0600
than interrupts IRQ7 to IRQ0 is generated. Software standby mode cannot be cleared if the
interrupt has been masked on the CPU side or has been designated as a DTC activation source.
• Clearing with the RES Pin or MRES Pin
When the RES pin or MRES pin is driven low, clock oscillation is started. At the same time as
clock oscillation starts, clocks are supplied to the entire this LSI chip. Note that the RES pin or
MRES pin must be held low until clock oscillation settles. When the RES pin or MRES pin
goes high, the CPU begins reset exception handling.
• Clearing with the STBY Pin
When the STBY pin is driven low, a transition is made to hardware standby mode.
24.4.3 Oscillation Settling Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
• Using a Crystal Oscillator
Set bits STS2 to STS0 so that the standby time is at least tOSC2 ms (the oscillation settling
time). Table 24.3 shows the standby times for different operating frequencies and settings of
bits STS2 to STS0.
• Using an External Clock
Any value can be set. Normally, minimum time is recommended.
Note: Do not set 16 states for standby time in the F-ZTAT version. 8192 states or more should
be set.
Table 24.3 Oscillation Settling Time Settings
STS2 STS1 STS0 Standby Time
20
MHz
*
1
16
MHz
*
1
13
MHz
10
MHz
8 MHz
*
2
6 MHz
*
2
4 MHz
*
2
2 MHz
*
2
Unit
0 0 0 8192 states 0.41 0.51 0.6 0.8 1.0 1.4 2.0 4.1 ms
1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2
1 0 32768 states 1.6 2.0 2.5 3.3 4.1 5.5 8.2 16.4
1 65536 states 3.3 4.1 5.0 6.6 8.2 10.9 16.4 32.8
1 0 0 131072 states 6.6 8.2 10.1 13.1 16.4 21.8 32.8 65.5
1 262144 states 13.1 16.4 20.2 26.2 32.8 43.7 65.5 131.1
1 0 Reserved ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
1 16 states 0.8 1.0 1.2 1.6 2.0 2.7 4.0 8.0 µs
: Recommended time setting
Notes: 1. Supported only by the H8S/2239 Group.
2. The H8S/2258 Group is out of operation.