Manualshelf

Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 100 (14x14) 16-Bit 13 MHz I/O number 72
851852853854855856857858859860
Section 24 Power-Down Modes
Rev. 6.00 Mar. 18, 2010 Page 792 of 982
REJ09B0054-0600
24.3.2 Exiting Sleep Mode
Sleep mode is exited by any interrupt, or signals at the RES pin, MRES pin, or STBY pin.
• Exiting Sleep Mode by Interrupts
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
• Exiting Sleep Mode by RES Pin or MRES Pin
Setting the RES pin or MRES pin level low selects the reset state. After the stipulated reset
input duration, driving the RES pin or MRES pin high starts the CPU performing reset
exception processing.
• Exiting Sleep Mode by STBY Pin
When the STBY pin level is driven low, a transition is made to hardware standby mode.
24.4 Software Standby Mode
24.4.1 Transition to Software Standby Mode
A transition is made to software standby mode when the SLEEP instruction is executed while the
SSBY bit in SBYCR = 1 and the LSON bit in LPWRCR = 0, and the PSS bit in TCSR_1
(WDT_1) = 0. In this mode, the CPU, on-chip peripheral modules, and system clock oscillator all
stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
peripheral modules other than SCI and the A/D converter, and the states of I/O ports are retained.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
24.4.2 Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ7 to IRQ0), or by
means of the MRES pin or STBY pin.
• Clearing with an Interrupt
When an NMI, or IRQ7 to IRQ0 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to
the entire this LSI chip, software standby mode is cleared, and interrupt exception handling is
started.
When clearing software standby mode with an IRQ7 to IRQ0 interrupt, set the corresponding
enable bit/pin function switching bit to 1 and ensure that no interrupt with a higher priority