Datasheet

Section 24 Power-Down Modes
Rev. 6.00 Mar. 18, 2010 Page 788 of 982
REJ09B0054-0600
Bit Bit Name Initial Value R/W Description
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
These bits select the MCU wait time for clock
settling to cancel software standby mode, watch
mode, or subactive mode.
With a crystal resonator (tables 24.3, 27.5, 27.17,
27.30, 27.42, 27.53), select a wait time of t
OSC2
ms
(oscillation settling time) or more, depending on the
operating frequency. With an external clock, there
are no specific wait requirements.
000: Standby time = 8192 states
001: Standby time = 16384 states
010: Standby time = 32768 states
011: Standby time = 65536 states
100: Standby time = 131072 states
101: Standby time = 262144 states
110: Reserved
111: Standby time = 16 states
*
3 OPE 1 R/W Output Port Enable
Specifies whether the output of the address bus and
bus control signals (CS7 to CS0, AS, RD, HWR, and
LWR) should be retained or driven to the high
impedance state, when shifting to software standby
mode, watch mode, or direct transition.
0: High impedance
1: Output is retained.
2 to 0 — All 0 — Reserved
These bits are always read as 0 and cannot be
modified.
Note: * Don’t set 16 states for standby time in the F-ZTAT version. 8192 states or more should
be set.