Datasheet

Section 24 Power-Down Modes
Rev. 6.00 Mar. 18, 2010 Page 787 of 982
REJ09B0054-0600
24.1 Register Description
The following registers relates to the power-down modes. For details on system clock control
register (SCKCR), refer to section 23.1.1, System Clock Control Register (SCKCR). For details
on low power control register (LPWRCR), refer to section 23.1.2, Low Power Control Register
(LPWRCR). For details on timer control status register (TCSR_1), refer to section 13.3.2, Timer
Control/Status Register (TCSR).
• Standby control register (SBYCR)
• Module stop control register A (MSTPCRA)
• Module stop control register B (MSTPCRB)
• Module stop control register C (MSTPCRC)
• Low power control register (LPWRCR)
• System clock control register (SCKCR)
• Timer control status register (TCSR_1)
24.1.1 Standby Control Register (SBYCR)
SBYCR performs power-down mode control.
Bit Bit Name Initial Value R/W Description
7 SSBY 0 R/W Software Standby
Specifies transition destination when the SLEEP
instruction is executed.
0: Shifts to sleep mode when the SLEEP instruction
is executed in high-speed mode or medium-speed
mode.
Shifts to subsleep mode when the SLEEP
instruction is executed in subactive mode.
1: Shifts to software standby mode, subactive mode,
and watch mode when the SLEEP instruction is
executed in high-speed mode or medium-speed
mode.
Shifts to watch mode or high-speed mode when
the SLEEP instruction is executed in subactive
mode.
Note that the value of the SSBY bit does not change
even when software standby mode is canceled and
making normal operation mode transition by
executing an external interrupt. To clear this bit, 0
should be written to.