Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 781 of 982
REJ09B0054-0600
23.7.2 Handling Pins when Subclock Not Required
If no subclock is required, connect the OSC1 pin to Vss and leave OSC2 open, as shown in figure
23.10. The SUBSTP bit in LPWRCR must be set to 1. If the SUBSTP bit is not set to 1, transitions
to the power-down modes may not complete normally.
On the H8S/2237 and H8S/2227 Group, the OSC1 pin should be connected to VCC.
OSC1
OSC2
Open
Figure 23.10 Pin Handling when Subclock Not Required
23.8 Subclock Waveform Generation Circuit
To eliminate noise from the subclock input to OSCI, the subclock is sampled using the dividing
clock φ. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section
23.1.2, Low Power Control Register (LPWRCR).
No sampling is performed in sub-active mode, sub-sleep mode, or watch mode.
23.9 Usage Notes
23.9.1 Note on Crystal Resonator
As various characteristics related to the crystal resonator are closely linked to the user’s board
design, thorough evaluation is necessary on the user’s part, using the resonator connection
examples shown in this section as a guide. As the resonator circuit ratings will depend on the
floating capacitance of the resonator and the mounting circuit, the ratings should be determined in
consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the
maximum rating is not applied to the oscillator pin.