Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 779 of 982
REJ09B0054-0600
23.3 Duty Adjustment Circuit
The duty adjustment circuit is valid when oscillation frequency is more than 5 MHz. The duty
adjustment circuit adjusts clock output fr/m the system clock oscillator to generate the system
clock (φ).
23.4 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
23.5 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the clock supplied to the bus master by setting the
bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from system clock (φ), or
medium-speed clocks (φ/2, φ/4, φ/8, φ/16, φ/32).
23.6 System Clock when Using IEBus
When using the IEBus, the system clock must be set to either 12 MHz or 12.58 MHz. When the
IEBus is not used, the system clock can be set to an arbitrary frequency between 10 MHz to 13.5
MHz.
Note: IEBus is supported only by the H8S/2258 Group.