Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 777 of 982
REJ09B0054-0600
Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (5)
(H8S/2239 Group)
F-ZTAT and Masked ROM Masked ROM
V
CC
= 3.0 V to
3.6 V
V
CC
= 2.7 V to
3.6 V
V
CC
= 2.2 V to
3.6 V
Item Symbol Min Max Min Max Min Max Unit Test Conditions
External clock input
low pulse width
t
EXL
25 — 31.25 — 80 — ns
External clock input
high pulse width
t
EXH
25 — 31.25 — 80 — ns
External clock
rise time
t
EXr
— 5 — 6.25 — 15 ns
Figure 23.5
External clock
fall time
t
EXf
— 5 — 6.25 — 15 ns
Note: When a duty adjustment circuit is not used, maximum operating frequency is lowered
according to the input waveform.
(Example: When t
EXL
= t
EXH
= 25 ns, t
EXr
= t
EXf
= 5 ns, clock cycle time = 60 ns, and maximum
operating frequency = 16.6 MHz)
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 23.5 External Clock Input Timing
23.2.3 Notes on Switching External Clock
When two or more external clocks (e.g.:10 MHz and 2 MHz) are used as the system clock, input
clock should be switched in software standby mode.
An example of external clock switching circuit is shown in figure 23.6. An example of external
clock switching timing is shown in figure 23.7.