Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 773 of 982
REJ09B0054-0600
Table 23.3 External Clock Input Conditions (2) (H8S/2238B, H8S/2236B)
F-ZTAT Masked ROM
V
CC
= 3.0 V to 5.5 V V
CC
= 2.7 V to 5.5 V
Item Symbol
Min Max Min Max Unit Test Conditions
External clock input
low pulse width
t
EXL
30 — 30 — ns
External clock input
high pulse width
t
EXH
30 — 30 — ns
External clock rise
time
t
EXr
— 7 — 7 ns
External clock fall
time
t
EXf
— 7 — 7 ns
Figure 23.5
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHz Clock low pulse
width
t
CL
80 — 80 — ns φ < 5 MHz
Figure
27.10
t
CH
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHz Clock high pulse
width
80 — 80 — ns φ < 5 MHz
Table 23.3 External Clock Input Conditions (3) (H8S/2238R, H8S/2236R)
F-ZTAT Masked ROM
V
CC
= 2.7 V to 3.6 V V
CC
= 2.2 V to 3.6 V
Item Symbol
Min Max Min Max Unit Test Conditions
External clock input
low pulse width
t
EXL
30 — 65 — ns
External clock input
high pulse width
t
EXH
30 — 65 — ns
External clock rise
time
t
EXr
— 7 — 15 ns
External clock fall
time
t
EXf
— 7 — 15 ns
Figure 23.5
0.4 0.6 0.35 0.65 t
cyc
φ ≥ 5 MHz Clock low pulse
width
t
CL
80 — 70 — ns φ < 5 MHz
Figure
27.10
t
CH
0.4 0.6 0.35 0.65 t
cyc
φ ≥ 5 MHz Clock high pulse
width
80 — 70 — ns φ < 5 MHz