Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 772 of 982
REJ09B0054-0600
EXTAL
XTAL
EXTAL
XTAL
External clock input
Open
External clock input
(a) XTAL pin left open
(b) Complementary clock input at XTAL pin
Figure 23.4 External Clock Input (Examples)
Table 23.3 shows the input conditions for the external clock. Table 23.4 shows the input
conditions for the external clock when duty adjustment circuit is not used.
Table 23.3 External Clock Input Conditions (1) (H8S/2258 Group)
V
CC
= 4.0 V to 5.5 V
Item Symbol Min Max Unit Test Conditions
External clock input low
pulse width
t
EXL
30 — ns
External clock input high
pulse width
t
EXH
30 — ns
External clock rise time t
EXr
— 7 ns
External clock fall time t
EXf
— 7 ns
Figure 23.5
Clock low pulse width t
CL
0.4 0.6 t
CYC
Figure 27.10
Clock high pulse width t
CH
0.4 0.6 t
CYC