Datasheet

Section 23 Clock Pulse Generator
Rev. 6.00 Mar. 18, 2010 Page 765 of 982
REJ09B0054-0600
Section 23 Clock Pulse Generator
This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master
clock, and internal clocks. The clock pulse generator consists of an oscillator, duty adjustment
circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit,
subclock oscillator, and wave formation circuit. A block diagram of the clock pulse generator is
shown in figure 23.1.
Legend:
LPWRCR:
SCKCR:
Low-power control register
System clock control register
EXTAL
XTAL
Duty
adjustment
circuit
Medium-
speed
clock divider
System
clock
oscillator
Clock
selection
circuit
φSUB
WDT_1 count clock
Internal clock to
peripheral modules
System clock φ pin
Bus master cloc
k
to CPU and DTC
and DMAC
*
φ/2 to
φ/32
φ
SCK2 to SCK0
SCKCR
RFCUT
OSC1
OSC2
Waveform
Generation
Circuit
Subclock
oscillator
LPWRCR
Bus
master
clock
selection
circuit
Note: * Supported only by the H8S/2239 Group.
Figure 23.1 Block Diagram of Clock Pulse Generator
Frequency changes are performed by software by settings in the low-power control register
(LPWRCR) and system clock control register (SCKCR).