Datasheet

Section 20 Flash Memory (F-ZTAT Version)
Rev. 6.00 Mar. 18, 2010 Page 741 of 982
REJ09B0054-0600
Erase start
Set EBR1 (2)
Enable WDT
Disable WDT
Read verify data
Increment address
Verify data = all 1?
Last address of block?
All erase block erased?
Set block start address as verify address
H'FF dummy write to verify address
SWE1 bit in FLMCR1 ← 1
n = 1
ESU1 bit in FLMCR1 ← 1
E1 bit in FLMCR1 ← 1 start erasing
stop erasing
tsswe: Wait 1 μs
tsswe: Wait 100 μs
E1 bit in FLMCR1 ← 0
EV1 bit in FLMCR ← 1
tse: Wait 10 ms
ESU1 bit in FLMCR1 ← 0
tce: Wait 10 μs
tcesu: Wait 10 μs
tsev: Wait 20 μs
EV1 bit in FLMCR ← 0
n ← n + 1
tcer: Wait 4 μs
SWE1 bit in FLMCR1 ← 0
tcswe: Wait 100 μs
EV1 bit in FLMCR ← 0
n ≥ 100?
*
5
tcer: Wait 4 μs
SWE1 bit in FLMCR1 ← 0
tcswe: Wait 100 μs
Erase failure
End of erasing
tsevr: Wait 2 μs
No
Yes
Yes
No
No
No
Yes
Yes
*
1
*
3
*
2
*
5
*
4
Erasing should be
done to a block
1. Pre-writing (all erase block data are cleared to 0) is not necessary.
2. Verify data is read out in 16 bit size (word access).
3. Erasing block register (EBR) can be set about 1 bit at a time.
Do not specify 2 bits or more.
4. Erasing is performed block by block. When multiple blocks must be erased,
erase each lock one by one.
5. This is a recommended value. To change it, consult tables 27.12, 27.25, 27.37, 27.49, and 27.59 and select
a new value such that the erase time (tE), wait time after E1 bit setting (tse), and maximum erase count (N)
do not exceed the maximum values indicated.
Notes:
Figure 20.12 Erase/Erase-Verify Flowchart