Datasheet

Section 17 A/D Converter
Rev. 6.00 Mar. 18, 2010 Page 699 of 982
REJ09B0054-0600
ADST
ADF
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 0
(AN0)
Notes:
Continuous A/D conversion
State of channel 1
(AN1)
State of channel 3
(AN3)
State of channel 2
(AN2)
Clear
*
1
Clear
*
1
Set
*
1
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
A/D conversion time
A/D conversion 1
A/D conversion 2
A/D conversion 4
A/D conversion 3
A/D conversion 5
*
2
A/D conversion result 1
A/D conversion result 4
A/D conversion result 2
A/D conversion result 3
1. Vertical arrows indicate instructions executed by software.
2. Data currently being converted is ignored.
Figure 17.4 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)
17.5.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
D
) has passed after the ADST bit is set to 1, then
starts conversion. Figure 17.5 shows the A/D conversion timing. Table 17.3 shows the A/D
conversion time.
As indicated in figure 17.5, the A/D conversion time (t
CONV
) includes t
D
and the input sampling time
(t
SPL
). The length of t
D
varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 17.3.
In scan mode, the values given in table 17.3 apply to the first conversion time. The values given in
table 17.4 apply to the second and subsequent conversions.