Datasheet

Section 17 A/D Converter
Rev. 6.00 Mar. 18, 2010 Page 693 of 982
REJ09B0054-0600
17.3.2 A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit Bit Name
Initial
Value R/W Description
7 ADF 0 R/(W)
*
A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the data transfer controller (DTC) is
activated by an ADI interrupt and DISEL in DTC
is 0 with the transfer counter not being 0
6 ADIE 0 R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled
when 1 is set
5 ADST 0 R/W A/D Start
Clearing this bit to 0 stops A/D conversion, and the
A/D converter enters the wait state.
Setting this bit to 1 starts A/D conversion. In single
mode, this bit is cleared to 0 automatically when
conversion on the specified channel is complete. In
scan mode, conversion continues sequentially on
the specified channels until this bit is cleared to 0 by
software, a reset, software standby mode, hardware
standby mode, or module stop mode.
The ADST bit can be set to 1 by software, a timer
conversion start trigger, or the A/D external trigger
input pin (ADTRG).