Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 687 of 982
REJ09B0054-0600
SCL
BC2 to BC0
Transmit data A
SDA
7 6 5 4 3 2 1 0 7 6 5
1 2 3 4 5 6 7 8 9 12 3
0
IRIC flag can not be cleared
IRIC flag can be cleared
IRIC flag can be cleared
9
A
IRIC
(sampling
example)
Confirm
SCL = L
IRIC clear
IRIC clear when
BC2 to BC0 ≥ 2
Transmit data
Figure 16.28 IRIC Flag Clearing Timing in Wait Operation
17. Interrupt during Module Stop Mode
When the module is stopped in the state that an interrupt is requested, the interrupt source of
the CPU or activation source of the DTC is not cleared. Be sure to enter module stop mode by
disabling the interrupt beforehand.
16.6.1 Module Stop Mode Setting
IIC operation can be disabled or enabled using the module stop control register. The initial setting
is for IIC operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 24, Power-Down Modes.