Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 677 of 982
REJ09B0054-0600
Table 16.7 I
2
C Bus Timing (SCL and SDA Output)
Item Symbol Output Timing Unit Notes
SCL output cycle time t
SCLO
28 t
cyc
to 256 t
cyc
ns
SCL output high pulse width t
SCLHO
0.5 t
SCLO
ns
SCL output low pulse width t
SCLLO
0.5 t
SCLO
ns
SDA output bus free time t
BUFO
0.5 t
SCLO
– 1 t
cyc
ns
Start condition output hold time t
STAHO
0.5 t
SCLO
– 1 t
cyc
ns
Retransmission start condition
output setup time
t
STASO
1 t
SCLO
ns
Stop condition output setup time t
STOSO
0.5 t
SCLO
+ 2 t
cyc
ns
Data output setup time (master) t
SDASO
1 t
SCLLO
– 3 t
cyc
ns
Data output setup time (slave)
*
1
1 t
SCLL
– 3 t
cyc
ns
Data output setup time (slave)
*
2
1 t
SCLL
– (6 t
cyc
or 12 t
cyc
)
*
3
ns
Figure 27.34
Data output hold time t
SDAHO
3 t
cyc
ns
Notes: 1. Not supported by the H8S/2258 Group.
2. Supported only by the H8S/2258 Group.
3. 6 t
cyc
when IICX is 0, 12 t
cyc
when IICX is 1.
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
cyc
, as shown in table 27.22 (H8S/2239 Group)
and table 27.34 (H8S/2238B and H8S/2236B). Note that the I
2
C bus interface AC timing
specifications will not be met with a system clock frequency of less than 5 MHz.
5. The I
2
C bus interface specification for the SCL rise time t
sr
is under 1000 ns (300 ns for high-
speed mode). In master mode, the I
2
C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t
sr
(the time for SCL to go from low to V
IH
) exceeds
the time determined by the input clock of the I
2
C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table in
table 16.8.