Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 660 of 982
REJ09B0054-0600
Set WAIT = 1 (ICMR)
Clear IRIC flag in ICCR
Set ACKB = 0 (ICSR)
Set TRS = 0 (ICCR)
Read ICDR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
IRTR = 1?
IRIC = 1?
No
No
Yes
Yes
No
Yes
Yes
No
Yes
No
[1] Set to receive mode.
[2] Receive start, dummy read.
[5] Read receive data.
[6] Clear IRIC flag (cancel wait state).
[7] Set acknowledge data for final receive.
[8] Wait time until TRS setting.
[9] Set TRS to generate stop condition.
[10] Read receive data.
[14] Clear IRIC flag (cancel wait state).
[16] Read final receive data.
[15] Cancel wait mode
Clear IRIC flag. (IRIC flag should be cleared when WAIT = 0.)
[17] Generate stop condition.
[13] Data receive completed judgment.
[12] Receive wait state (IRIC set at falling edge of 8th clock cycle)
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle).
[3] Receive wait state (IRIC set at falling edge of 8th clock cycle)
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle).
[4] Data receive completed judgment.
Last receive?
Read ICDR
Read ICDR
[11] Clear IRIC flag (cancel wait state).
Clear IRIC flag in ICCR
Set ACKB = 1 (ICSR)
1 clock cycle wait state
Set TRS = 1 (ICCR)
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Set WAIT = 0 (ICMR)
Clear IRIC flag in ICCR
Read ICDR
IRTR = 1?
IRIC = 1?
Write BBSY = 0
and SCP = 0 (ICCR)
End
Master receive mode
Figure 16.10 Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1)
(Example)