Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 655 of 982
REJ09B0054-0600
16.4.2 Initial Setting
At startup the following procedure is used to initialize the IIC.
Clear module stop.
Start initialization
Set IICE = 1 (SCRX)
Set ICE = 0 (ICCR)
Set SAR and SARX
Set ICE = 1 (ICCR)
Set ICSR
Set SCRX
Set ICMR
Set ICCR
Set MSTPB4 = 0 (IIC0)
MSTPB3 = 0 (IIC1)
(MSTPCRB)
Enable CPU access by IIC control register and data register.
Enable SAR and SARX access.
Set transfer format for 1st slave address, 2nd slave address,
and IIC (SVA8 to SVA0, FS, SVAX6 to SVAX0, FSX).
Enable IMCR and IMDR access. Use SCL and SDA pins is IIC
port.
Set acknowledge bit (ACKB).
Set transfer rate (IICX).
Set transfer format, wait insertion, and transfer rate (MLS,
WAIT, CKS2 to CKS0).
Set interrupt enable, transfer mode, and acknowledge
judgment (IEIC, MST, TRS, ACKE).
Transmit/receive start
Figure 16.6 Flowchart for IIC Initialization (Example)
Note: The ICMR register should be written to only after transmit or receive operations have
completed.
Writing to the ICMR register while a transmit or receive operation is in progress could
cause an erroneous value to be written to bit counter bits BC2 to BC0. This could result in
improper operation.
16.4.3 Master Transmit Operation
In I
2
C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.