Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 643 of 982
REJ09B0054-0600
16.3.5 Serial Control Register X (SCRX)
SCRX controls the IIC operating modes.
Bit Bit Name
Initial
Value R/W Description
7 ⎯ 0 R/W Reserved
The initial value should not be changed.
6
5
IICX1
IICX0
0
0
R/W
R/W
I
2
C Transfer Rate Select 1 and 0
Selects the transfer rate in master mode, together with bits
CKS2 to CKS0 in ICMR. Refer to table 16.3.
IICX1 controls IIC_1 and IICX0 controls IIC_0.
4 IICE 0 R/W I
2
C Master Enable
Controls CPU access to the IIC data register and control
registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR).
0: CPU access to the IIC data register and control registers
is disabled.
1: CPU access to the IIC data register and control registers
is enabled.
3 FLSHE 0 R/W For details on this bit, refer to section 20.5.7, Serial Control
Register X (SCRX).
2 to 0 ⎯ All 0 R/W Reserved
The initial value should not be changed.