Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 639 of 982
REJ09B0054-0600
16.3.2 Slave Address Register (SAR)
SAR selects the slave address and selects the transfer format. SAR can be written and read only
when the ICE bit is cleared to 0 in ICCR.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Slave Address 6 to 0
Sets a slave address.
0 FS 0 R/W Selects the transfer format together with the FSX bit in
SARX. Refer to table 16.2.
16.3.3 Second Slave Address Register (SARX)
SARX stores the second slave address and selects the transfer format. SARX can be written and
read only when the ICE bit is cleared to 0 in ICCR.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Second Slave Address 6 to 0
Sets the second slave address.
0 FSX 1 R/W Selects the transfer format together with the FS bit in SAR.
Refer to table 16.2.