Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 638 of 982
REJ09B0054-0600
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
ICDR can be written and read only when the ICE bit is set to 1 in ICCR. The value of ICDR is
undefined after a reset.
The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF flags affects the status of the interrupt flags.
Bit Bit Name
Initial
Value R/W Description
⎯ TDRE ⎯ ⎯ Transmit Data Register Empty
[Setting conditions]
• In transmit mode, when a start condition is detected in
the bus line state after a start condition is issued in
master mode with the I
2
C bus format or serial format
selected
• When data is transferred from ICDRT to ICDRS
• When a switch is made from receive mode to transmit
mode after detection of a start condition
[Clearing conditions]
• When transmit data is written in ICDR in transmit mode
• When a stop condition is detected in the bus line state
after a stop condition is issued with the I
2
C bus format
or serial format selected
• When a stop condition is detected with the I
2
C bus
format selected
• In receive mode
⎯ RDRF ⎯ ⎯ Receive Data Register Full
[Setting condition]
When data is transferred from ICDRS to ICDRR
[Clearing condition]
When ICDR (ICDRR) receive data is read in receive mode