Datasheet

Section 1 Overview
Rev. 6.00 Mar. 18, 2010 Page 8 of 982
REJ09B0054-0600
PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8
VCC VCC VSS VSS
PA3/A19
PA2/A18
PA1/A17
PA0/A16
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3 / A11
PB2/A10
PB1/A9
PB0/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P36
P35/SCK1/IRQ
5
P34/RxD1
P33/TxD1
P32/SCK0/IRQ
4
P31/RxD0
P30/TxD0
P97
P96
P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
Vref AVCC AVSS
P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1/IRQ0 P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD P70/TMRI01/TMCI01/CS4 P71/CS5 P72/TMO0/CS6 P73/TMO1/CS7 P74/MRES P75/SCK3 P76/RxD3 P77/TxD3
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/IRQ7
PG0/IRQ6
PF7/ φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
PF2/WAIT
PF1/BACK/BUZZ
PF0/BREQ/IRQ2
MD2
MD1
MD0
EXTAL
XTAL
OSC1
OSC2
STBY
RES
NMI
FWE
H8S/2000 CPU
Internal data bus
Port D
PC break
controller
(2 channels)
ROM
RAM
TPU (3 channels)
DTC
Interrupt
controller
Port E
Port 4Port 1 Port 7
Internal address bus
Port APort B
Bus controller
Port CPort 3Port 9
Port G
Port F
SCI (3 channels)
8-bit timer (2 channels)
A/D converter (8 channels)
WDT0
WDT1
(subclock)
Subclock
pulse
generator
System clock
pulse
generator
Peripheral data bus
Peripheral address bus
Figure 1.5 Internal Block Diagram of H8S/2227 Group