Datasheet

Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 585 of 982
REJ09B0054-0600
15.4 Operation in Asynchronous Mode
Figure 15.5 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). In
asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver
are independent units, enabling full-duplex communication. Both the transmitter and the receiver
also have a double-buffered structure, so that data can be read or written during transmission or
reception, enabling continuous data transfer. In asynchronous mode, the SCI performs
synchronization at the falling edge of the start bit in reception. The SCI samples the data on the
8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is
latched at the center of each bit.
The SCI_0 samples the data on the 4th pulse of a clock with a frequency of 8 times the length of
one bit when the ABCS bit in SEMR_0 is 1 (H8S/2239 Group only).
LSB
Start
bit
MSB
Idle state
(mark state)
Stop bit
0
Transmit/receive data
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 1
Serial
data
Parity
bit
1 bit 1 or
2 bits
7 or 8 bits
1 bit,
or none
One unit of transfer data (character or frame)
Figure 15.5 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
15.4.1 Data Transfer Format
Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 15.5, Multiprocessor Communication Function.