Datasheet

Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 571 of 982
REJ09B0054-0600
15.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 15.2 The Relationships between the N Setting in BRR and Bit Rate B
Communication
Mode
ABCS bit
*
Bit Rate Error
0
B =
64 × 2
2n−1
× (N + 1)
φ × 10
6
Error (%) = {
B × 64 × 2
2n−1
× (N + 1)
−1 } × 100
φ × 10
6
Asynchronous
Mode
1
B =
32 × 2
2n−1
× (N + 1)
φ × 10
6
Error (%) = {
B × 32 × 2
2n−1
× (N + 1)
−1 } × 100
φ × 10
6
Clocked
Synchronous
Mode
⎯
B =
8 × 2
2n−1
× (N + 1)
φ × 10
6
⎯
Smart Card
Interface Mode
⎯
B =
S × 2
2n+1
× (N + 1)
φ × 10
6
Error (%) = {
B × S × 2
2n+1
× (N + 1)
−1 } × 100
φ × 10
6
Legend:
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
Note: * If the ABCS bit is set to 1, SCI_0 on the H8S/2239 Group only valid bit rate.
SMR Setting SMR Setting
CKS1 CKS0
Clock
Source n BCP1 BCP0 S
0 0 φ 0 0 0 32
0 1 φ/4 1 0 1 64
1 0 φ/16 2 1 0 372
1 1 φ/64 3 1 1 256