Datasheet

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 532 of 982
REJ09B0054-0600
Dn H MA SA CF LF D1 D2 Dn-1 Dn
IECTR
RE
RSS
CMX
MRQ
SRQ
SRE
RxRDY
RxS
RxF
IERxI (RxRDY)
(TO DTC)
IERxI (RxRDY)
(TO CPU)
IERSI
(TO CPU)
IEFLG
IEFLG
IERSR
Interrupt
(1)
(2)
(2)
(7)
(7)
(7)
(3) (4)
(3) (4) (5)
(5)
(6)
Broadcast reception Slave reception
H: Header, MA: Master address field, SA: Slave address field,
CF: Control field, LF: Message length field, D1, D2,..., Dn-1, Dn: Data field
DTC transfer
of 1st byte
DTC transfer
of (n-2)th byte
DTC transfer
of (n-1)th byte
DTC transfer
of nth byte
Figure 14.9 Slave Reception Operation Timing
(4) When an Error Occurs in Broadcast Reception (DEE = 1)
Figure 14.10 shows an example in which a receive error occurs because the receive preparation
cannot be completed (the RxRDY flag is not cleared) until the control field is received in
broadcast reception after the slave reception while the DEE bit is set to 1.
Note: The same as the case in which the RE bit is not set before the control field reception.