Datasheet

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 527 of 982
REJ09B0054-0600
14.4 Operation Descriptions
14.4.1 Master Transmit Operation
This section describes an example of master transmission using the DTC after slave reception.
(1) IEB Initialization
(a) Setting the IEBus Control Register (IECTR)
Enable the IEBus pins, select the signal polarity, and select a clock supplied to the IEB. Clear
the LUEE bit to 0 since the transfer is performed by the DTC.
(b) Setting the IEBus Master Unit Address Registers 1 and 2 (IEAR1 and IEAR2)
Specify the master unit address and specify the communications mode in IEAR1.
(c) Setting the IEBus Slave Address Setting Registers 1 and 2 (IESA1 and IESA2)
Specify the communications destination slave unit address.
(d) Setting the IEBus Master Control register (IEMCR)
Select broadcast/normal communications, specify the number of retransfer counts at arbitration
loss, and specify the control bits.
(e) Setting the IEBus Transmit Message Length Register (IETBFL)
Specify the message length bits.
(f) Setting the IEBus Transmit/Runaway Interrupt Enable Register (IEIET)
Enable TxRDY (IETxI), TxS, TxF, and TxE (IETSI) interrupts.
The above registers can be specified in any order. (The register specification order does not affect
the IEB operation.)
(2) DTC Initialization
1. Set the start address of the RAM which stores the register information necessary for the DTC
transfer in the vector address (H'000004D4) to be accessed when a DTC transfer request is
generated.
2. Set the following data from the start address of the RAM.
⎯ Transfer source address (SAR): Start address of the RAM which stores data to be
transmitted in the data field.
⎯ Transfer destination address (DAR): Address (H'FFF808) of the IEBus transmit buffer
register (IETBR)
⎯ Transfer count (CRA): The same value as the IETBFL contents
3. Set DTCEG5 in the DTC enable register G (DTCERG) to enable the TxRDY interrupt
(IETxI).