Datasheet

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 524 of 982
REJ09B0054-0600
14.3.22 IEBus Receive Interrupt Enable Register (IEIER)
IEIER enables/disables IERSR reception ready, receive start, transmit/receive normal completion,
and receive completion with an error interrupts.
Bit Bit Name
Initial
Value
R/W Description
7 RxRDYE 0 R/W Receive Data Ready Interrupt Enable
Enables/disables a receive data ready interrupt.
0: Disables a receive data ready (RxRDY) interrupt
1: Enables a receive data ready (RxRDY) interrupt
6 to 3 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be modified.
2 RxSE 0 R/W Receive Start Interrupt Enable
Enables/disables a receive start (RxS) interrupt.
0: Disables a receive start (RxS) interrupt
1: Enables a receive start (RxS) interrupt
1 RxFE 0 R/W Receive Normal Completion Enable
Enables or disables a receive normal completion (RxF)
interrupt.
0: Disables a receive normal completion (RxF) interrupt
1: Enables a receive normal completion (RxF) interrupt
0 RxEE 0 R/W Receive Error Termination Interrupt Enable
Enables or disables a receive error termination (RxE)
interrupt.
0: Disables a receive error termination (RxE) interrupt
1: Enables a receive error termination (RxE) interrupt
14.3.23 IEBus Receive Error Flag Register (IEREF)
IEREF checks the source of an RxE interrupt indicated in IERSR. This register detects an overrun
error, timing error, overflow of a maximum number of bytes in one frame, and parity error.
These flags become valid when the receive start flag (RxS) is set to 1. If an error occurs before the
RxS flag is set to 1, the IEB terminates the communications and enters the wait state. In this case,
these flags will not be set and the RxE flag is not set.