Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 100 (14x14) 16-Bit 13 MHz I/O number 72

Rev. 6.00 Mar. 18, 2010 Page lvi of lx

REJ09B0054-0600

Table 15.10 Serial Transfer Formats (Asynchronous Mode).....................................................586

Table 15.11 SSR Status Flags and Receive Data Handling........................................................593

Table 15.12 Interrupt Sources of Serial Communication Interface Mode..................................623

Table 15.13 Interrupt Sources in Smart Card Interface Mode....................................................624

Section 16 I

C Bus Interface (IIC) (Option)

Table 16.1

Pin Configuration...................................................................................................636

Table 16.2 Transfer Format......................................................................................................640

Table 16.3 I

C Transfer Rate....................................................................................................642

Table 16.4 Flags and Transfer States .......................................................................................648

Table 16.5 Flags and Transfer States .......................................................................................673

Table 16.6 IIC Interrupt Source ...............................................................................................676

Table 16.7 I

C Bus Timing (SCL and SDA Output) ................................................................677

Table 16.8 Permissible SCL Rise Time (t

) Values .................................................................678

Table 16.9 I

C Bus Timing (with Maximum Influence of t

) ..............................................679

Section 17 A/D Converter

Table 17.1

Pin Configuration...................................................................................................691

Table 17.2 Analog Input Channels and Corresponding ADDR Registers................................692

Table 17.3 A/D Conversion Time (Single Mode)....................................................................700

Table 17.4 A/D Conversion Time (Scan Mode).......................................................................700

Table 17.5 A/D Converter Interrupt Source.............................................................................701

Table 17.6 Analog Pin Specifications......................................................................................706

Section 18 D/A Converter

Table 18.1

Pin Configuration...................................................................................................708

Table 18.2 D/A Conversion Control ........................................................................................709

Section 20 Flash Memory (F-ZTAT Version)

Table 20.1

Differences between Boot Mode and User Program Mode....................................717

Table 20.2 Pin Configuration...................................................................................................724

Table 20.3 Setting On-Board Programming Modes.................................................................732

Table 20.4 Boot Mode Operation.............................................................................................734

Table 20.5 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate

Is Possible...............................................................................................................734

Table 20.6 Flash Memory Operating States.............................................................................745

Table 20.7 Registers Present in F-ZTAT Version but Absent in Masked ROM Version ........751

Section 22 PROM

Table 22.1

Selecting PROM Mode ..........................................................................................755